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Except for one instance the spd_addr.h were now very tiny, there's not much point in keeping that stuff in an extra file. The only user of those files is the romstage.c file anyway. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 |
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.. | ||
chip.h | ||
cmos.layout | ||
devicetree.cb | ||
get_bus_conf.c | ||
hda_verb.h | ||
irq_tables.c | ||
Kconfig | ||
mainboard.c | ||
mb_sysconf.h | ||
mptable.c | ||
README | ||
resourcemap.c | ||
romstage.c |
There are a number of outstanding issues: * I'm seeing toolchain issues. I can't get this tree to compile correctly with gcc 4.3 (32 bit) - there is an optimization issue where certain parts of the CBFS code execute very slowly. With gcc 3.4 (32 bit) that slowness disappears. This is probably not a problem related to this port specifically. * setting CONFIG_DEFAULT_CONSOLE_LOGLEVEL lower than 8 simply hangs the boot shortly after the warm reset triggered by the MCP55 code. I think this too might be a toolchain problem (but I see it on gcc 3.4 as well as 4.3). * during startup, the CPU cores talk through each other on serial for a while. Again, not an issue specific to this port. * to avoid very slow LZMA decompression I use this port with LZMA compression disabled in CBFS. I'm not sure what's causing this particular slowness. See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/052107.html Ward, 2009-09-22 mansoor@iwavesystems.com said, about the last issue: Try enabling CONFIG_XIP_ROM_BASE. It solved the same problem for me in my board. So, that's a todo.