d7a696d0f2
These are the changes for the AMD Persimmon mainboard required to support the update of the AMD Family 14 cpu to rev C0. There are many warning fixes; the agesa- wrapper.c file has been changed to fix the amdinitlate and amdlaterunaptask routines, and more. Change-Id: I6de43379a2819cea5169db5f21d4841f9a4942a7 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/137 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
122 lines
2.9 KiB
C
122 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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#include <arch/pirq_routing.h>
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#include <cpu/amd/amdfam14.h>
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static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
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u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
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u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
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u8 slot, u8 rfu)
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{
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pirq_info->bus = bus;
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pirq_info->devfn = devfn;
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pirq_info->irq[0].link = link0;
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pirq_info->irq[0].bitmap = bitmap0;
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pirq_info->irq[1].link = link1;
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pirq_info->irq[1].bitmap = bitmap1;
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pirq_info->irq[2].link = link2;
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pirq_info->irq[2].bitmap = bitmap2;
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pirq_info->irq[3].link = link3;
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pirq_info->irq[3].bitmap = bitmap3;
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pirq_info->slot = slot;
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pirq_info->rfu = rfu;
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}
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extern u8 bus_isa;
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extern u8 bus_sb800[2];
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extern unsigned long sbdn_sb800;
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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struct irq_routing_table *pirq;
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struct irq_info *pirq_info;
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u32 slot_num;
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u8 *v;
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u8 sum = 0;
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int i;
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get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
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/* Align the table to be 16 byte aligned. */
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addr += 15;
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addr &= ~15;
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/* This table must be betweeen 0xf0000 & 0x100000 */
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printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
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pirq = (void *)(addr);
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v = (u8 *) (addr);
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pirq->signature = PIRQ_SIGNATURE;
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pirq->version = PIRQ_VERSION;
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pirq->rtr_bus = bus_sb800[0];
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pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4;
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pirq->exclusive_irqs = 0;
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pirq->rtr_vendor = 0x1002;
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pirq->rtr_device = 0x4384;
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pirq->miniport_data = 0;
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memset(pirq->rfu, 0, sizeof(pirq->rfu));
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pirq_info = (void *)(&pirq->checksum + 1);
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slot_num = 0;
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/* pci bridge */
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write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
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0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
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0);
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pirq_info++;
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slot_num++;
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pirq->size = 32 + 16 * slot_num;
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for (i = 0; i < pirq->size; i++)
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sum += v[i];
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sum = pirq->checksum - sum;
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if (sum != pirq->checksum) {
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pirq->checksum = sum;
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}
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printk(BIOS_INFO, "write_pirq_routing_table done.\n");
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return (unsigned long)pirq_info;
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}
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