Xavi Drudis Ferran 26f97d2cf9 Improving BKDG implementation of P-states, ... CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Looking at BKDG the process for updating Pstate Nb vid after warn reset seemed more similar to the codethat was there fo pvi than the one for svi, so I called the pvi function passing a pvi/svi flag. I don't find documentation on why should UpdateSinglePlaneNbVid() be called in PVI, but since I can't test it, I leave it as it was. This patch showed some progress beyond fidvid in my boar,d but only sometimes, most times it just didn't work. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1		2011-02-28 03:08:06 +00:00
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amd	Improving BKDG implementation of P-states,	2011-02-28 03:08:06 +00:00
intel	[i945] Add SPD adress mapping	2011-02-21 09:39:17 +00:00
via	__PRE_RAM__ is defined by the makefile	2010-12-27 13:30:39 +00:00
Kconfig	Drop remainders of PPC port	2009-10-28 19:40:46 +00:00
Makefile.inc	Drop remainders of PPC port	2009-10-28 19:40:46 +00:00