c70e9fc233
- Consistently use the same wording and formatting for all license headers. - Remove useless whitespace, add missing whitespace, fix indentation. - Add missing "This file is part of the coreboot project." where needed. - Change "(C) Copyright John Doe" to "Copyright (C) John Doe" for consistency. - Add some missing "(C)" strings and copyright years where needed. - Move random comments and file descriptions out of the license header. - Drop incorrect file descriptions completely (e.g. lpc47m10x/Makefile.inc). There should be no changes in _content_ of the license headers, if you spot such changes that's a bug, please report! Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
75 lines
2 KiB
C
75 lines
2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
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#define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
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struct southbridge_intel_i82801gx_config {
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/**
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* Interrupt Routing configuration
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* If bit7 is 1, the interrupt is disabled.
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*/
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uint8_t pirqa_routing;
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uint8_t pirqb_routing;
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uint8_t pirqc_routing;
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uint8_t pirqd_routing;
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uint8_t pirqe_routing;
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uint8_t pirqf_routing;
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uint8_t pirqg_routing;
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uint8_t pirqh_routing;
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/**
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* GPI Routing configuration
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*
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* Only the lower two bits have a meaning:
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* 00: No effect
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* 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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* 10: SCI (if corresponding GPIO_EN bit is also set)
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* 11: reserved
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*/
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uint8_t gpi0_routing;
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uint8_t gpi1_routing;
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uint8_t gpi2_routing;
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uint8_t gpi3_routing;
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uint8_t gpi4_routing;
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uint8_t gpi5_routing;
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uint8_t gpi6_routing;
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uint8_t gpi7_routing;
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uint8_t gpi8_routing;
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uint8_t gpi9_routing;
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uint8_t gpi10_routing;
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uint8_t gpi11_routing;
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uint8_t gpi12_routing;
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uint8_t gpi13_routing;
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uint8_t gpi14_routing;
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uint8_t gpi15_routing;
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uint32_t gpe0_en;
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uint16_t alt_gp_smi_en;
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/* IDE configuration */
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uint32_t ide_legacy_combined;
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uint32_t ide_enable_primary;
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uint32_t ide_enable_secondary;
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uint32_t sata_ahci;
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};
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extern struct chip_operations southbridge_intel_i82801gx_ops;
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#endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */
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