6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
119 lines
3.6 KiB
C
119 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/pci_ids.h>
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#include <soc/pci_devs.h>
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#include <soc/reg_access.h>
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/* USB Phy Registers */
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#define USB2_GLOBAL_PORT 0x4001
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#define USB2_PLL1 0x7F02
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#define USB2_PLL2 0x7F03
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#define USB2_COMPBG 0x7F04
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/* EHCI Packet Buffer OUT/IN Thresholds, values in number of DWORDs */
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#define EHCI_OUT_THRESHOLD_VALUE 0x7f
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#define EHCI_IN_THRESHOLD_VALUE 0x7f
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/* Platform init USB device interrupt masks */
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#define V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG (0x0000007f)
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#define V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG \
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(B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK \
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| B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK)
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/* In order to configure the USB PHY to use clk120 (ickusbcoreclk) as PLL
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* reference clock and Port2 as a USB device port, the following sequence must
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* be followed
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*/
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static const struct reg_script ehci_init_script[] = {
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/* Set packet buffer OUT/IN thresholds */
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REG_MMIO_RMW32(R_IOH_EHCI_INSNREG01,
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~(B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK
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| B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK),
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(EHCI_OUT_THRESHOLD_VALUE
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<< B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)
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| (EHCI_IN_THRESHOLD_VALUE
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<< B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)),
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/* Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b.
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* For port 0 & 1 as host and port 2 as device.
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*/
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REG_USB_RXW(USB2_GLOBAL_PORT, ~(BIT8 | BIT7 | BIT1), (BIT8 | BIT7)),
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/*
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* Sighting #4930653 Required BIOS change on Disconnect vref to change
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* to 600mV.
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*/
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REG_USB_RXW(USB2_COMPBG, ~(BIT10 | BIT9 | BIT8 | BIT7),
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(BIT10 | BIT7)),
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/* Sideband register write to USB AFE (Phy)
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* (pllbypass) to bypass/Disable PLL before switch
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*/
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REG_USB_OR(USB2_PLL2, BIT29),
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/* Sideband register write to USB AFE (Phy)
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* (coreclksel) to select 120MHz (ickusbcoreclk) clk source.
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* (Default 0 to select 96MHz (ickusbclk96_npad/ppad))
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*/
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REG_USB_OR(USB2_PLL1, BIT1),
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/* Sideband register write to USB AFE (Phy)
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* (divide by 8) to achieve internal 480MHz clock
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* for 120MHz input refclk. (Default: 4'b1000 (divide by 10) for 96MHz)
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*/
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REG_USB_RXW(USB2_PLL1, ~(BIT6 | BIT5 | BIT4 | BIT3), BIT6),
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/* Sideband register write to USB AFE (Phy)
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* Clear (pllbypass)
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*/
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REG_USB_AND(USB2_PLL2, ~BIT29),
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/* Sideband register write to USB AFE (Phy)
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* Set (startlock) to force the PLL FSM to restart the lock
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* sequence due to input clock/freq switch.
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*/
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REG_USB_OR(USB2_PLL2, BIT24),
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REG_SCRIPT_END
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};
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static const struct reg_script usb_device_port_init_script[] = {
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/* Mask and clear controller interrupts */
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REG_MMIO_WRITE32(R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG,
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V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG),
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REG_MMIO_WRITE32(R_IOH_USBDEVICE_D_INTR_UDC_REG,
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V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG),
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/* Mask and clear end point interrupts */
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REG_MMIO_WRITE32(R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG,
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V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG),
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REG_MMIO_WRITE32(R_IOH_USBDEVICE_EP_INTR_UDC_REG,
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V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG),
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REG_SCRIPT_END
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};
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static void init(struct device *dev)
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{
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if ((dev->path.pci.devfn & 7) == EHCI_FUNC) {
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printk(BIOS_INFO, "Initializing USB PLLs\n");
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reg_script_run_on_dev(dev, ehci_init_script);
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} else {
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printk(BIOS_INFO, "Initializing USB device port\n");
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reg_script_run_on_dev(dev, usb_device_port_init_script);
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}
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}
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static struct device_operations device_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = init,
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};
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static const struct pci_driver driver __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = EHCI_DEVID,
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};
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