a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
110 lines
2.7 KiB
C
110 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <boardid.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/i2c.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <reset.h>
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#include "pmic.h"
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enum {
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AS3722_I2C_ADDR = 0x40
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};
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struct as3722_init_reg {
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u8 reg;
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u8 val;
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u8 delay;
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};
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static struct as3722_init_reg init_list[] = {
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{AS3722_SDO0, 0x3C, 1},
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{AS3722_SDO1, 0x32, 0},
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{AS3722_LDO3, 0x59, 0},
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{AS3722_SDO2, 0x3C, 0},
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{AS3722_SDO3, 0x00, 0},
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{AS3722_SDO4, 0x00, 0},
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{AS3722_SDO5, 0x50, 0},
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{AS3722_SDO6, 0x28, 1},
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{AS3722_LDO0, 0x8A, 0},
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{AS3722_LDO1, 0x00, 0},
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{AS3722_LDO2, 0x10, 0},
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{AS3722_LDO4, 0x00, 0},
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{AS3722_LDO5, 0x00, 0},
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{AS3722_LDO6, 0x00, 0},
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{AS3722_LDO7, 0x00, 0},
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{AS3722_LDO9, 0x00, 0},
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{AS3722_LDO10, 0x00, 0},
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{AS3722_LDO11, 0x00, 1},
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};
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static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
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{
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if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) {
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printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
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__func__, reg, val);
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/* Reset the SoC on any PMIC write error */
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hard_reset();
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} else {
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if (do_delay)
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udelay(500);
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}
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}
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static void pmic_slam_defaults(unsigned bus)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(init_list); i++) {
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struct as3722_init_reg *reg = &init_list[i];
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pmic_write_reg(bus, reg->reg, reg->val, reg->delay);
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}
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}
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void pmic_init(unsigned bus)
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{
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/*
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* Don't need to set up VDD_CORE - already done - by OTP
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* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
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* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
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*/
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/* Restore PMIC POR defaults, in case kernel changed 'em */
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pmic_slam_defaults(bus);
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/* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
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pmic_write_reg(bus, 0x00, 0x50, 1);
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/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
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pmic_write_reg(bus, 0x06, 0x28, 1);
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/*
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* First set +1.2V_GEN_AVDD to 1.2V, then enable the +1.2V_GEN_AVDD
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* regulator.
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*/
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pmic_write_reg(bus, 0x12, 0x10, 1);
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/*
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* Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
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* the value (register 0x20 bit 4)
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*/
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pmic_write_reg(bus, 0x0c, 0x07, 0);
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pmic_write_reg(bus, 0x20, 0x10, 1);
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}
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