273a8dca1f
Use shared gpio code from common folder, except for INTEL_LYNXPOINT_LP, which has it's own gpio code. Needs test on real hardware ! Change-Id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13615 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
56 lines
1.6 KiB
Makefile
56 lines
1.6 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
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ramstage-y += pch.c
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ramstage-y += azalia.c
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ramstage-y += lpc.c
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ramstage-y += pci.c
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ramstage-y += pcie.c
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ramstage-y += sata.c
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ramstage-y += usb_ehci.c
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ramstage-y += usb_xhci.c
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ramstage-y += me_9.x.c
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ramstage-y += smbus.c
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ramstage-y += hda_verb.c
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ramstage-$(CONFIG_INTEL_LYNXPOINT_LP) += serialio.c
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ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
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ramstage-y += rcba.c
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ramstage-y += me_status.c
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ramstage-y += reset.c
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ramstage-y += watchdog.c
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ramstage-y += acpi.c
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ramstage-$(CONFIG_ELOG) += elog.c
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ramstage-y += ../common/spi.c
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smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c
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romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c
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romstage-y += reset.c early_spi.c rcba.c
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ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
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romstage-y += lp_gpio.c
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ramstage-y += lp_gpio.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += lp_gpio.c
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endif
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endif
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