a02e4a0428
As far as I know, the Cortex-A53 cores in RK3399 are of a newer revision that is not affected by ARM erratum 843419. If it was, the workaround would also need to be enabled in libpayload and Chrome OS userspace, which it currently isn't. I assume this was just incorrectly copied over from another SoC and we can safely remove it. BRANCH=None BUG=chrome-os-partner:56700 TEST=Booted Kevin. Change-Id: I5b1534c954a6d985499b481738723cabbdc07253 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4891cc866583532ee3dcb1a5ad5b81670eb0743d Original-Change-Id: Iadb57428f8727ce0e563204723644e2c79e3007c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376363 Original-Commit-Queue: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16702 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
27 lines
546 B
Text
27 lines
546 B
Text
config SOC_ROCKCHIP_RK3399
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bool
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default n
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select ARCH_BOOTBLOCK_ARMV8_64
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select ARCH_RAMSTAGE_ARMV8_64
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select ARCH_ROMSTAGE_ARMV8_64
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select ARCH_VERSTAGE_ARMV8_64
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select ARM64_USE_ARM_TRUSTED_FIRMWARE
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select BOOTBLOCK_CONSOLE
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select DRIVERS_UART_8250MEM_32
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select GENERIC_UDELAY
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select HAVE_MONOTONIC_TIMER
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select UART_OVERRIDE_REFCLK
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if SOC_ROCKCHIP_RK3399
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config CHROMEOS
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select RETURN_FROM_VERSTAGE
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select SEPARATE_VERSTAGE
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select VBOOT_OPROM_MATTERS
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select VBOOT_STARTS_IN_BOOTBLOCK
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config PMIC_BUS
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int
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default -1
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endif
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