664 lines
21 KiB
C
664 lines
21 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2000 Silicon Integrated System Corporation
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* Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __FLASH_H__
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#define __FLASH_H__ 1
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#if defined(__GLIBC__)
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#include <sys/io.h>
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#endif
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#include <unistd.h>
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#include <stdint.h>
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#include <stdio.h>
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#if (defined(__MACH__) && defined(__APPLE__))
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#define __DARWIN__
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#endif
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#if defined(__FreeBSD__)
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#include <machine/cpufunc.h>
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#define off64_t off_t
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#define lseek64 lseek
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#define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0)
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#define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0)
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#define OUTL(x, y) do { u_int tmp = (y); outl(tmp, (x)); } while (0)
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#define INB(x) __extension__ ({ u_int tmp = (x); inb(tmp); })
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#define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); })
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#define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); })
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#else
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#if defined(__DARWIN__)
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#include <DirectIO/darwinio.h>
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#define off64_t off_t
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#define lseek64 lseek
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#endif
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#define OUTB outb
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#define OUTW outw
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#define OUTL outl
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#define INB inb
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#define INW inw
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#define INL inl
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#endif
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#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
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struct flashchip {
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const char *vendor;
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const char *name;
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/*
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* With 32bit manufacture_id and model_id we can cover IDs up to
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* (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's
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* Identification code.
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*/
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uint32_t manufacture_id;
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uint32_t model_id;
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int total_size;
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int page_size;
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/*
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* Indicate if flashrom has been tested with this flash chip and if
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* everything worked correctly.
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*/
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uint32_t tested;
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int (*probe) (struct flashchip *flash);
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int (*erase) (struct flashchip *flash);
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int (*write) (struct flashchip *flash, uint8_t *buf);
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int (*read) (struct flashchip *flash, uint8_t *buf);
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/* Some flash devices have an additional register space. */
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volatile uint8_t *virtual_memory;
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volatile uint8_t *virtual_registers;
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};
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#define TEST_UNTESTED 0
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#define TEST_OK_PROBE (1<<0)
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#define TEST_OK_READ (1<<1)
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#define TEST_OK_ERASE (1<<2)
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#define TEST_OK_WRITE (1<<3)
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#define TEST_OK_PR (TEST_OK_PROBE|TEST_OK_READ)
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#define TEST_OK_PREW (TEST_OK_PROBE|TEST_OK_READ|TEST_OK_ERASE|TEST_OK_WRITE)
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#define TEST_OK_MASK 0x0f
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#define TEST_BAD_PROBE (1<<4)
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#define TEST_BAD_READ (1<<5)
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#define TEST_BAD_ERASE (1<<6)
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#define TEST_BAD_WRITE (1<<7)
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#define TEST_BAD_PREW (TEST_BAD_PROBE|TEST_BAD_READ|TEST_BAD_ERASE|TEST_BAD_WRITE)
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#define TEST_BAD_MASK 0xf0
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extern struct flashchip flashchips[];
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/*
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* Please keep this list sorted alphabetically by manufacturer. The first
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* entry of each section should be the manufacturer ID, followed by the
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* list of devices from that manufacturer (sorted by device IDs).
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*
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* All LPC/FWH parts (parallel flash) have 8-bit device IDs if there is no
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* continuation code.
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* SPI parts have 16-bit device IDs if they support RDID.
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*/
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#define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */
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#define ALLIANCE_ID 0x52 /* Alliance Semiconductor */
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#define AMD_ID 0x01 /* AMD */
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#define AM_29F002BT 0xB0
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#define AM_29F002BB 0x34
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#define AM_29F040B 0xA4
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#define AM_29LV040B 0x4F
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#define AM_29F016D 0xAD
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#define AMIC_ID 0x7F37 /* AMIC */
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#define AMIC_ID_NOPREFIX 0x37 /* AMIC */
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#define AMIC_A25L40P 0x2013
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#define AMIC_A29002B 0x0d
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#define AMIC_A29002T 0x8c
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#define AMIC_A29040B 0x86
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#define AMIC_A49LF040A 0x9d
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#define ASD_ID 0x25 /* ASD, not listed in JEP106W */
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#define ASD_AE49F2008 0x52
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#define ATMEL_ID 0x1F /* Atmel */
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#define AT_25DF021 0x4300
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#define AT_25DF041A 0x4401
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#define AT_25DF081 0x4502
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#define AT_25DF161 0x4602
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#define AT_25DF321 0x4700 /* also 26DF321 */
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#define AT_25DF321A 0x4701
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#define AT_25DF641 0x4800
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#define AT_25F512A 0x65 /* Needs special RDID. AT25F512A_RDID 15 1d */
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#define AT_25F512B 0x6500
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#define AT_25FS010 0x6601
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#define AT_25FS040 0x6604
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#define AT_26DF041 0x4400
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#define AT_26DF081 0x4500 /* guessed, no datasheet available */
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#define AT_26DF081A 0x4501
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#define AT_26DF161 0x4600
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#define AT_26DF161A 0x4601
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#define AT_26DF321 0x4700 /* also 25DF321 */
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#define AT_26F004 0x0400
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#define AT_29C040A 0xA4
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#define AT_29C020 0xDA
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#define AT_45BR3214B /* No ID available */
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#define AT_45CS1282 0x2920
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#define AT_45D011 /* No ID available */
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#define AT_45D021A /* No ID available */
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#define AT_45D041A /* No ID available */
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#define AT_45D081A /* No ID available */
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#define AT_45D161 /* No ID available */
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#define AT_45DB011 /* No ID available */
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#define AT_45DB011B /* No ID available */
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#define AT_45DB011D 0x2200
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#define AT_45DB021A /* No ID available */
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#define AT_45DB021B /* No ID available */
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#define AT_45DB021D 0x2300
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#define AT_45DB041A /* No ID available */
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#define AT_45DB041D 0x2400
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#define AT_45DB081A /* No ID available */
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#define AT_45DB081D 0x2500
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#define AT_45DB161 /* No ID available */
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#define AT_45DB161B /* No ID available */
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#define AT_45DB161D 0x2600
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#define AT_45DB321 /* No ID available */
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#define AT_45DB321B /* No ID available */
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#define AT_45DB321C 0x2700
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#define AT_45DB321D 0x2701 /* Buggy data sheet */
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#define AT_45DB642 /* No ID available */
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#define AT_45DB642D 0x2800
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#define AT_49F002N 0x07 /* for AT49F002(N) */
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#define AT_49F002NT 0x08 /* for AT49F002(N)T */
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#define CATALYST_ID 0x31 /* Catalyst */
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#define EMST_ID 0x8C /* EMST / EFST Elite Flash Storage */
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#define EMST_F49B002UA 0x00
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/*
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* EN25 chips are SPI, first byte of device ID is memory type,
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* second byte of device ID is log(bitsize)-9.
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* Vendor and device ID of EN29 series are both prefixed with 0x7F, which
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* is the continuation code for IDs in bank 2.
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* Vendor ID of EN25 series is NOT prefixed with 0x7F, this results in
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* a collision with Mitsubishi. Mitsubishi once manufactured flash chips.
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* Let's hope they are not manufacturing SPI flash chips as well.
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*/
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#define EON_ID 0x7F1C /* EON Silicon Devices */
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#define EON_ID_NOPREFIX 0x1C /* EON, missing 0x7F prefix */
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#define EN_25B05 0x2010 /* 2^19 kbit or 2^16 kByte */
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#define EN_25B10 0x2011
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#define EN_25B20 0x2012
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#define EN_25B40 0x2013
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#define EN_25B80 0x2014
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#define EN_25B16 0x2015
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#define EN_25B32 0x2016
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#define EN_29F512 0x7F21
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#define EN_29F010 0x7F20
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#define EN_29F040A 0x7F04
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#define EN_29LV010 0x7F6E
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#define EN_29LV040A 0x7F4F /* EN_29LV040(A) */
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#define EN_29F002T 0x7F92
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#define EN_29F002B 0x7F97
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#define FUJITSU_ID 0x04 /* Fujitsu */
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#define MBM29F400BC 0xAB
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#define MBM29F400TC 0x23
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#define MBM29F004BC 0x7B
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#define MBM29F004TC 0x77
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#define HYUNDAI_ID 0xAD /* Hyundai */
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#define IMT_ID 0x7F1F /* Integrated Memory Technologies */
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#define IM_29F004B 0xAE
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#define IM_29F004T 0xAF
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#define INTEL_ID 0x89 /* Intel */
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#define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */
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/*
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* MX25 chips are SPI, first byte of device ID is memory type,
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* second byte of device ID is log(bitsize)-9.
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* Generalplus SPI chips seem to be compatible with Macronix
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* and use the same set of IDs.
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*/
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#define MX_ID 0xC2 /* Macronix (MX) */
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#define MX_25L512 0x2010 /* 2^19 kbit or 2^16 kByte */
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#define MX_25L1005 0x2011
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#define MX_25L2005 0x2012
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#define MX_25L4005 0x2013 /* MX25L4005{,A} */
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#define MX_25L8005 0x2014
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#define MX_25L1605 0x2015 /* MX25L1605{,A,D} */
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#define MX_25L3205 0x2016 /* MX25L3205{,A} */
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#define MX_25L6405 0x2017 /* MX25L3205{,D} */
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#define MX_25L1635D 0x2415
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#define MX_25L3235D 0x2416
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#define MX_29F002B 0x34
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#define MX_29F002T 0xB0
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#define MX_29LV002CB 0x5A
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#define MX_29LV002CT 0x59
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#define MX_29LV004CB 0xB6
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#define MX_29LV004CT 0xB5
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#define MX_29LV008CB 0x37
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#define MX_29LV008CT 0x3E
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#define MX_29F040C 0xA4
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#define MX_29F200CB 0x57
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#define MX_29F200CT 0x51
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#define MX_29F400CB 0xAB
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#define MX_29F400CT 0x23
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#define MX_29LV040C 0x4F
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#define MX_29LV128DB 0x7A
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#define MX_29LV128DT 0x7E
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#define MX_29LV160DB 0x49 /* Same as MX29LV161DB/MX29LV160CB */
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#define MX_29LV160DT 0xC4 /* Same as MX29LV161DT/MX29LV160CT */
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#define MX_29LV320DB 0xA8 /* Same as MX29LV321DB */
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#define MX_29LV320DT 0xA7 /* Same as MX29LV321DT */
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#define MX_29LV400CB 0xBA
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#define MX_29LV400CT 0xB9
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#define MX_29LV800CB 0x5B
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#define MX_29LV800CT 0xDA
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#define MX_29LV640DB 0xCB /* Same as MX29LV640EB */
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#define MX_29LV640DT 0xC9 /* Same as MX29LV640ET */
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#define MX_29SL402CB 0xF1
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#define MX_29SL402CT 0x70
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#define MX_29SL800CB 0x6B /* Same as MX29SL802CB */
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#define MX_29SL800CT 0xEA /* Same as MX29SL802CT */
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/*
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* Programmable Micro Corp is listed in JEP106W in bank 2, so it should
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* have a 0x7F continuation code prefix.
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*/
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#define PMC_ID 0x7F9D /* PMC */
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#define PMC_ID_NOPREFIX 0x9D /* PMC, missing 0x7F prefix */
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#define PMC_25LV512 0x7B
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#define PMC_25LV010 0x7C
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#define PMC_25LV020 0x7D
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#define PMC_25LV040 0x7E
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#define PMC_25LV080B 0x13
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#define PMC_25LV016B 0x14
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#define PMC_39LV512 0x1B
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#define PMC_39F010 0x1C /* also Pm39LV010 */
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#define PMC_39LV020 0x3D
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#define PMC_39LV040 0x3E
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#define PMC_39F020 0x4D
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#define PMC_39F040 0x4E
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#define PMC_49FL002 0x6D
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#define PMC_49FL004 0x6E
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#define SHARP_ID 0xB0 /* Sharp */
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#define SHARP_LHF00L04 0xCF
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/*
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* Spansion was previously a joint venture of AMD and Fujitsu.
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* S25 chips are SPI. The first device ID byte is memory type and
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* the second device ID byte is memory capacity.
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*/
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#define SPANSION_ID 0x01 /* Spansion */
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#define SPANSION_S25FL016A 0x0214
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/*
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* SST25 chips are SPI, first byte of device ID is memory type, second
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* byte of device ID is related to log(bitsize) at least for some chips.
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*/
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#define SST_ID 0xBF /* SST */
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#define SST_25WF512 0x2501
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#define SST_25WF010 0x2502
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#define SST_25WF020 0x2503
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#define SST_25WF040 0x2504
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#define SST_25VF512A_REMS 0x48 /* REMS or RES opcode */
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#define SST_25VF010_REMS 0x49 /* REMS or RES opcode */
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#define SST_25VF020_REMS 0x43 /* REMS or RES opcode */
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#define SST_25VF040_REMS 0x44 /* REMS or RES opcode */
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#define SST_25VF040B 0x258D
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#define SST_25VF040B_REMS 0x8D /* REMS or RES opcode */
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#define SST_25VF080_REMS 0x80 /* REMS or RES opcode */
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#define SST_25VF080B 0x258E
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#define SST_25VF080B_REMS 0x8E /* REMS or RES opcode */
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#define SST_25VF016B 0x2541
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#define SST_25VF032B 0x254A
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#define SST_25VF032B_REMS 0x4A /* REMS or RES opcode */
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#define SST_26VF016 0x2601
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#define SST_26VF032 0x2602
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#define SST_27SF512 0xA4
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#define SST_27SF010 0xA5
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#define SST_27SF020 0xA6
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#define SST_27VF010 0xA9
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#define SST_27VF020 0xAA
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#define SST_28SF040 0x04
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#define SST_29EE512 0x5D
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#define SST_29EE010 0x07
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#define SST_29LE010 0x08 /* also SST29VE010 */
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#define SST_29EE020A 0x10
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#define SST_29LE020 0x12 /* also SST29VE020 */
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#define SST_29SF020 0x24
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#define SST_29VF020 0x25
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#define SST_29SF040 0x13
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#define SST_29VF040 0x14
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#define SST_39SF010 0xB5
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#define SST_39SF020 0xB6
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#define SST_39SF040 0xB7
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#define SST_39VF512 0xD4
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#define SST_39VF010 0xD5
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#define SST_39VF020 0xD6
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#define SST_39VF040 0xD7
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#define SST_49LF040B 0x50
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#define SST_49LF040 0x51
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#define SST_49LF020 0x61
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#define SST_49LF020A 0x52
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#define SST_49LF080A 0x5B
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#define SST_49LF002A 0x57
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#define SST_49LF003A 0x1B
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#define SST_49LF004A 0x60
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#define SST_49LF008A 0x5A
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#define SST_49LF004C 0x54
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#define SST_49LF008C 0x59
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#define SST_49LF016C 0x5C
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#define SST_49LF160C 0x4C
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/*
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* ST25P chips are SPI, first byte of device ID is memory type, second
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* byte of device ID is related to log(bitsize) at least for some chips.
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*/
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#define ST_ID 0x20 /* ST / SGS/Thomson */
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#define ST_M25P05A 0x2010
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#define ST_M25P10A 0x2011
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#define ST_M25P20 0x2012
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#define ST_M25P40 0x2013
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#define ST_M25P40_RES 0x12
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#define ST_M25P80 0x2014
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#define ST_M25P16 0x2015
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#define ST_M25P32 0x2016
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#define ST_M25P64 0x2017
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#define ST_M25P128 0x2018
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#define ST_M50FLW040A 0x08
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#define ST_M50FLW040B 0x28
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#define ST_M50FLW080A 0x80
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#define ST_M50FLW080B 0x81
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#define ST_M50FW002 0x29
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#define ST_M50FW040 0x2C
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#define ST_M50FW080 0x2D
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#define ST_M50FW016 0x2E
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#define ST_M50LPW116 0x30
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#define ST_M29F002B 0x34
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#define ST_M29F002T 0xB0 /* M29F002T / M29F002NT */
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#define ST_M29F400BT 0xD5
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#define ST_M29F040B 0xE2
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#define ST_M29W010B 0x23
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#define ST_M29W040B 0xE3
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#define SYNCMOS_ID 0x40 /* SyncMOS and Mosel Vitelic */
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#define S29C51001T 0x01
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#define S29C51002T 0x02
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#define S29C51004T 0x03
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#define S29C31004T 0x63
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#define TI_ID 0x97 /* Texas Instruments */
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/*
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* W25X chips are SPI, first byte of device ID is memory type, second
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* byte of device ID is related to log(bitsize).
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*/
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#define WINBOND_ID 0xDA /* Winbond */
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#define WINBOND_NEX_ID 0xEF /* Winbond (ex Nexcom) serial flash devices */
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#define W_25X10 0x3011
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#define W_25X20 0x3012
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#define W_25X40 0x3013
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#define W_25X80 0x3014
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#define W_25X16 0x3015
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#define W_25X32 0x3016
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#define W_25X64 0x3017
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#define W_29C011 0xC1
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#define W_29C020C 0x45
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#define W_29C040P 0x46
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#define W_29EE011 0xC1
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#define W_39V040FA 0x34
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#define W_39V040A 0x3D
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#define W_39V040B 0x54
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#define W_39V080A 0xD0
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#define W_39V080FA 0xD3
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#define W_39V080FA_DM 0x93
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#define W_49F002U 0x0B
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#define W_49V002A 0xB0
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#define W_49V002FA 0x32
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/* udelay.c */
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void myusec_delay(int time);
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void myusec_calibrate_delay();
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/* PCI handling for board/chipset_enable */
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struct pci_access *pacc;
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struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
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struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
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uint16_t card_vendor, uint16_t card_device);
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/* board_enable.c */
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void w836xx_ext_enter(uint16_t port);
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void w836xx_ext_leave(uint16_t port);
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unsigned char wbsio_read(uint16_t index, uint8_t reg);
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void wbsio_write(uint16_t index, uint8_t reg, uint8_t data);
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void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask);
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int board_flash_enable(const char *vendor, const char *part);
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void print_supported_boards(void);
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/* chipset_enable.c */
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int chipset_flash_enable(void);
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void print_supported_chipsets(void);
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extern unsigned long flashbase;
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typedef enum {
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BUS_TYPE_LPC,
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BUS_TYPE_ICH7_SPI,
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BUS_TYPE_ICH9_SPI,
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BUS_TYPE_IT87XX_SPI,
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BUS_TYPE_SB600_SPI,
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BUS_TYPE_VIA_SPI,
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BUS_TYPE_WBSIO_SPI
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} flashbus_t;
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extern flashbus_t flashbus;
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extern void *spibar;
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/* debug.c */
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extern int verbose;
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#define printf_debug(x...) { if (verbose) printf(x); }
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/* physmap.c */
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void *physmap(const char *descr, unsigned long phys_addr, size_t len);
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void physunmap(void *virt_addr, size_t len);
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/* flashrom.c */
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void map_flash_registers(struct flashchip *flash);
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/* layout.c */
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int show_id(uint8_t *bios, int size, int force);
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int read_romlayout(char *name);
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int find_romentry(char *name);
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int handle_romentries(uint8_t *buffer, uint8_t *content);
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/* lbtable.c */
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int coreboot_init(void);
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extern char *lb_part, *lb_vendor;
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/* spi.c */
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int probe_spi_rdid(struct flashchip *flash);
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int probe_spi_rdid4(struct flashchip *flash);
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int probe_spi_rems(struct flashchip *flash);
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int probe_spi_res(struct flashchip *flash);
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int spi_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr);
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int spi_write_enable();
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int spi_write_disable();
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int spi_chip_erase_60(struct flashchip *flash);
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int spi_chip_erase_c7(struct flashchip *flash);
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int spi_chip_erase_60_c7(struct flashchip *flash);
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int spi_chip_erase_d8(struct flashchip *flash);
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int spi_block_erase_52(const struct flashchip *flash, unsigned long addr);
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int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr);
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int spi_chip_write(struct flashchip *flash, uint8_t *buf);
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int spi_chip_read(struct flashchip *flash, uint8_t *buf);
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uint8_t spi_read_status_register();
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int spi_disable_blockprotect(void);
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void spi_byte_program(int address, uint8_t byte);
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int spi_nbyte_read(int address, uint8_t *bytes, int len);
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int spi_aai_write(struct flashchip *flash, uint8_t *buf);
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/* 82802ab.c */
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int probe_82802ab(struct flashchip *flash);
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int erase_82802ab(struct flashchip *flash);
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int write_82802ab(struct flashchip *flash, uint8_t *buf);
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/* am29f040b.c */
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int probe_29f040b(struct flashchip *flash);
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int erase_29f040b(struct flashchip *flash);
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int write_29f040b(struct flashchip *flash, uint8_t *buf);
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/* en29f002a.c */
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int probe_en29f002a(struct flashchip *flash);
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int erase_en29f002a(struct flashchip *flash);
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int write_en29f002a(struct flashchip *flash, uint8_t *buf);
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/* ichspi.c */
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int ich_init_opcodes();
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int ich_spi_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr);
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int ich_spi_read(struct flashchip *flash, uint8_t * buf);
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int ich_spi_write(struct flashchip *flash, uint8_t * buf);
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/* it87spi.c */
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extern uint16_t it8716f_flashport;
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int it87xx_probe_spi_flash(const char *name);
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int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr);
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int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf);
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int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf);
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/* sb600spi.c */
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int sb600_spi_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr);
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int sb600_spi_read(struct flashchip *flash, uint8_t *buf);
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int sb600_spi_write(struct flashchip *flash, uint8_t *buf);
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uint8_t sb600_read_status_register(void);
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extern uint8_t volatile *sb600_spibar;
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/* jedec.c */
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uint8_t oddparity(uint8_t val);
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void toggle_ready_jedec(volatile uint8_t *dst);
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void data_polling_jedec(volatile uint8_t *dst, uint8_t data);
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void unprotect_jedec(volatile uint8_t *bios);
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void protect_jedec(volatile uint8_t *bios);
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int write_byte_program_jedec(volatile uint8_t *bios, uint8_t *src,
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volatile uint8_t *dst);
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int probe_jedec(struct flashchip *flash);
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int erase_chip_jedec(struct flashchip *flash);
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int write_jedec(struct flashchip *flash, uint8_t *buf);
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int erase_sector_jedec(volatile uint8_t *bios, unsigned int page);
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int erase_block_jedec(volatile uint8_t *bios, unsigned int page);
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int write_sector_jedec(volatile uint8_t *bios, uint8_t *src,
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volatile uint8_t *dst, unsigned int page_size);
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/* m29f400bt.c */
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int probe_m29f400bt(struct flashchip *flash);
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int erase_m29f400bt(struct flashchip *flash);
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int block_erase_m29f400bt(volatile uint8_t *bios,
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volatile uint8_t *dst);
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int write_m29f400bt(struct flashchip *flash, uint8_t *buf);
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int write_coreboot_m29f400bt(struct flashchip *flash, uint8_t *buf);
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void toggle_ready_m29f400bt(volatile uint8_t *dst);
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void data_polling_m29f400bt(volatile uint8_t *dst, uint8_t data);
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void protect_m29f400bt(volatile uint8_t *bios);
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void write_page_m29f400bt(volatile uint8_t *bios, uint8_t *src,
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volatile uint8_t *dst, int page_size);
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/* mx29f002.c */
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int probe_29f002(struct flashchip *flash);
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int erase_29f002(struct flashchip *flash);
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int write_29f002(struct flashchip *flash, uint8_t *buf);
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/* pm49fl00x.c */
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int probe_49fl00x(struct flashchip *flash);
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int erase_49fl00x(struct flashchip *flash);
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int write_49fl00x(struct flashchip *flash, uint8_t *buf);
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/* sharplhf00l04.c */
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int probe_lhf00l04(struct flashchip *flash);
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int erase_lhf00l04(struct flashchip *flash);
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int write_lhf00l04(struct flashchip *flash, uint8_t *buf);
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void toggle_ready_lhf00l04(volatile uint8_t *dst);
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void data_polling_lhf00l04(volatile uint8_t *dst, uint8_t data);
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void protect_lhf00l04(volatile uint8_t *bios);
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/* sst28sf040.c */
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int probe_28sf040(struct flashchip *flash);
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int erase_28sf040(struct flashchip *flash);
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int write_28sf040(struct flashchip *flash, uint8_t *buf);
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/* sst39sf020.c */
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int probe_39sf020(struct flashchip *flash);
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int write_39sf020(struct flashchip *flash, uint8_t *buf);
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/* sst49lf040.c */
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int erase_49lf040(struct flashchip *flash);
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int write_49lf040(struct flashchip *flash, uint8_t *buf);
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/* sst49lfxxxc.c */
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int probe_49lfxxxc(struct flashchip *flash);
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int erase_49lfxxxc(struct flashchip *flash);
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int write_49lfxxxc(struct flashchip *flash, uint8_t *buf);
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/* sst_fwhub.c */
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int probe_sst_fwhub(struct flashchip *flash);
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int erase_sst_fwhub(struct flashchip *flash);
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int write_sst_fwhub(struct flashchip *flash, uint8_t *buf);
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/* w39v040c.c */
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int probe_w39v040c(struct flashchip *flash);
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int erase_w39v040c(struct flashchip *flash);
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int write_w39v040c(struct flashchip *flash, uint8_t *buf);
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/* w39V080fa.c */
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int probe_winbond_fwhub(struct flashchip *flash);
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int erase_winbond_fwhub(struct flashchip *flash);
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int write_winbond_fwhub(struct flashchip *flash, uint8_t *buf);
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/* w29ee011.c */
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int probe_w29ee011(struct flashchip *flash);
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/* w49f002u.c */
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int write_49f002(struct flashchip *flash, uint8_t *buf);
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/* wbsio_spi.c */
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int wbsio_check_for_spi(const char *name);
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int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
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int wbsio_spi_read(struct flashchip *flash, uint8_t *buf);
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int wbsio_spi_write(struct flashchip *flash, uint8_t *buf);
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/* stm50flw0x0x.c */
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int probe_stm50flw0x0x(struct flashchip *flash);
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int erase_stm50flw0x0x(struct flashchip *flash);
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int write_stm50flw0x0x(struct flashchip *flash, uint8_t *buf);
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#endif /* !__FLASH_H__ */
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