cdfb46240b
Previously MP table contained PCI_INT entries for PCI bus behind bridge 0:14.4 even if said PCI bridge function was disabled. Remove these as invalid, indeterminate bus number could cause conflicts. PCI_INT entries with bus_sb800[2], bus_hudson[2] and bus_yangtze[2] were invalid as there is no PCI bridge hardware on device 0:14.0. Remove these as invalid, indeterminate bus number could cause conflicts. Change-Id: Ie6a3807f64c8651cf9f732612e1aa7f376a3134f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6358 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
164 lines
4.7 KiB
C
164 lines
4.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <string.h>
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#include <stdint.h>
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/amd/amdfam15.h>
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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u32 apicid_sb700;
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u32 apicid_rd890;
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device_t dev;
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u32 dword;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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smp_write_processors(mc);
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mptable_write_buses(mc, NULL, &bus_isa);
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/*
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* AGESA v5 Apply apic enumeration rules
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* For systems with >= 16 APICs, put the IO-APICs at 0..n and
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* put the local-APICs at m..z
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* For systems with < 16 APICs, put the Local-APICs at 0..n and
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* put the IO-APICs at (n + 1)..z
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*/
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if (CONFIG_MAX_CPUS >= 16)
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apicid_sb700 = 0x0;
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else
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apicid_sb700 = CONFIG_MAX_CPUS + 1;
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apicid_rd890 = apicid_sb700 + 1;
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dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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if (dev) {
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/* Set sb700 IOAPIC ID */
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dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
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smp_write_ioapic(mc, apicid_sb700, 0x20, dword);
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/*
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* 00:12.0: PROG SATA : INT F
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* 00:13.0: INTA USB_0
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* 00:13.1: INTB USB_1
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* 00:13.2: INTC USB_2
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* 00:13.3: INTD USB_3
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* 00:13.4: INTC USB_4
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* 00:13.5: INTD USB2
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* 00:14.1: INTA IDE
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* 00:14.2: Prog HDA : INT E
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* 00:14.5: INTB ACI
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* 00:14.6: INTB MCI
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*/
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/* Set RS5650 IOAPIC ID */
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dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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if (dev) {
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pci_write_config32(dev, 0xF8, 0x1);
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dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
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smp_write_ioapic(mc, apicid_rd890, 0x20, dword);
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}
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}
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/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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#define IO_LOCAL_INT(type, intr, apicid, pin) \
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smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
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mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
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/* PCI interrupts are level triggered, and are
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* associated with a specific bus/device/function tuple.
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*/
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#define PCI_INT(bus, dev, int_sign, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin))
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/* SMBUS */
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//PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0
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/* HD Audio */
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PCI_INT(0x0, 0x14, 0x2, 0x10);
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/* USB */
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/* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */
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/* EHCI hard-wired to 02h, corresponding to using INTB# */
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/* USB1 */
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PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
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PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */
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PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */
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/* USB2 */
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PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */
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PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */
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PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */
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/* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */
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PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */
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/* SATA */
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PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
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/* PCI slots */
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dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
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if (dev && dev->enabled) {
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u8 bus_pci = dev->link_list->secondary;
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/* PCI_SLOT 0. */
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PCI_INT(bus_pci, 0x5, 0x0, 0x14);
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PCI_INT(bus_pci, 0x5, 0x1, 0x15);
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PCI_INT(bus_pci, 0x5, 0x2, 0x16);
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PCI_INT(bus_pci, 0x5, 0x3, 0x17);
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/* PCI_SLOT 1. */
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PCI_INT(bus_pci, 0x6, 0x0, 0x15);
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PCI_INT(bus_pci, 0x6, 0x1, 0x16);
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PCI_INT(bus_pci, 0x6, 0x2, 0x17);
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PCI_INT(bus_pci, 0x6, 0x3, 0x14);
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/* PCI_SLOT 2. */
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PCI_INT(bus_pci, 0x7, 0x0, 0x16);
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PCI_INT(bus_pci, 0x7, 0x1, 0x17);
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PCI_INT(bus_pci, 0x7, 0x2, 0x14);
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PCI_INT(bus_pci, 0x7, 0x3, 0x15);
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}
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
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IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
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/* There is no extension information... */
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0);
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return (unsigned long)smp_write_config_table(v);
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}
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