27c9762f95
This change splits the device operations for internal and external PCIe GPP bridges so that the external bridges use `pciexp_scan_bridge()` instead of `pci_scan_bridge()`. `pciexp_scan_bridge()` is required for external GPP bridges to enable ASPM on downstream devices if supported. BUG=b:162352484 TEST=Verified on Trembyle: $ lspci -s 1:00.0 -vvv | grep ASPM LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <4us, L1 <64u ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ice2aa3e4758adccf7b0b89d4222fc65a40761153 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
76 lines
1.9 KiB
C
76 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpigen.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pciexp.h>
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#include <device/pci_ids.h>
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#include <soc/pci_devs.h>
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#include <stdio.h>
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static const char *pcie_gpp_acpi_name(const struct device *dev)
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{
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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switch (dev->path.pci.devfn) {
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case PCIE_GPP_0_DEVFN:
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return "PBR0";
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case PCIE_GPP_1_DEVFN:
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return "PBR1";
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case PCIE_GPP_2_DEVFN:
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return "PBR2";
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case PCIE_GPP_3_DEVFN:
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return "PBR3";
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case PCIE_GPP_4_DEVFN:
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return "PBR4";
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case PCIE_GPP_5_DEVFN:
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return "PBR5";
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case PCIE_GPP_6_DEVFN:
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return "PBR6";
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case PCIE_GPP_A_DEVFN:
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return "PBRA";
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case PCIE_GPP_B_DEVFN:
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return "PBRB";
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}
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return NULL;
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}
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static struct device_operations internal_pcie_gpp_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.scan_bus = pci_scan_bridge,
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.reset_bus = pci_bus_reset,
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.acpi_name = pcie_gpp_acpi_name,
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.acpi_fill_ssdt = acpi_device_write_pci_dev,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSA,
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PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSB,
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0
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};
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static const struct pci_driver internal_pcie_gpp_driver __pci_driver = {
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.ops = &internal_pcie_gpp_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.devices = pci_device_ids,
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};
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static struct device_operations external_pcie_gpp_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.scan_bus = pciexp_scan_bridge,
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.reset_bus = pci_bus_reset,
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.acpi_name = pcie_gpp_acpi_name,
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.acpi_fill_ssdt = acpi_device_write_pci_dev,
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};
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static const struct pci_driver external_pcie_gpp_driver __pci_driver = {
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.ops = &external_pcie_gpp_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP,
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};
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