Shawn Nematbakhsh 287522749e lynxpoint: Add configuration option for SATA gen3 DTLE registers ... Allow DTLE DATA / EDGE registers to be configured in board-specific devicetree. Change-Id: I82307d08c9cf73461db3ac7fb875a4fe70d6f9ea Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65716 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4475 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>		2013-12-21 12:03:00 +01:00
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arch	arm: Don't use const pointers with the write functions	2013-12-21 10:48:57 +01:00
console	snprintf: lockless operation	2013-12-07 19:27:53 +01:00
cpu	exynos5420: Fix some clock settings	2013-12-21 10:49:04 +01:00
device	Add Kconfig options to override Subsystem Vendor and Device ID	2013-12-21 12:02:40 +01:00
drivers	tpm: provide explicit tpm register access	2013-12-21 10:49:11 +01:00
ec	chromeec: Add event methods for EC requested throttle	2013-12-21 12:02:14 +01:00
include	Add a specific post code for S3 resume failures	2013-12-21 12:02:43 +01:00
lib	Add simple hexdump function	2013-12-21 08:25:44 +01:00
mainboard	wtm2: disable SDcard USB port	2013-12-21 12:02:53 +01:00
northbridge	haswell: add option to change DqPinsInterleaved	2013-12-21 12:02:56 +01:00
southbridge	lynxpoint: Add configuration option for SATA gen3 DTLE registers	2013-12-21 12:03:00 +01:00
superio	Correct file permissions.	2013-12-07 00:39:09 +01:00
vendorcode	chromeos: Check for recovery reason code in shared data	2013-12-21 07:28:37 +01:00
Kconfig	Add GRUB2 payload to build system	2013-11-19 01:07:25 +01:00