Martin Roth e18e6427d0 src: change coreboot to lowercase ... The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>		2017-06-07 12:09:15 +02:00
..
include	arch: Unify basic cache clearing API	2017-05-30 22:19:50 +02:00
boot.c	riscv: start to use the configstring functions	2016-11-12 19:23:22 +01:00
bootblock.S	riscv: get SBI calls to work	2017-01-16 00:26:08 +01:00
id.ld	arch/riscv: Add missing license headers	2016-01-18 02:14:03 +01:00
id.S	src/arch/riscv/id.S: Don't hardcode the strings	2016-08-04 17:17:38 +02:00
Kconfig	riscv: start to use the configstring functions	2016-11-12 19:23:22 +01:00
Makefile.inc	riscv: start to use the configstring functions	2016-11-12 19:23:22 +01:00
mcall.c	riscv: Move mcall numbers to mcall.h, adjust their names	2017-01-16 06:15:53 +01:00
misc.c	arch/riscv: Add missing license headers	2016-01-18 02:14:03 +01:00
payload.S	riscv: change payload() to pass the config string pointer as arg0	2016-11-13 00:16:37 +01:00
prologue.inc
sbi.S	src: change coreboot to lowercase	2017-06-07 12:09:15 +02:00
stages.c	arch: remove stage_exit()	2016-02-11 23:12:06 +01:00
tables.c	lib: add common write_tables() implementation	2016-04-21 20:49:05 +02:00
trap_handler.c	src: change coreboot to lowercase	2017-06-07 12:09:15 +02:00
trap_util.S	riscv: get SBI calls to work	2017-01-16 00:26:08 +01:00
virtual_memory.c	riscv: enable counters via m[us]counteren	2016-12-20 00:10:33 +01:00