903b40a8a4
To call dev_find_slot(0, xx) in romstage can produce invalid results since PCI bus enumeration has not been progressed yet. Replace this with method that relies on bus topology that walks the root bus only. Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
83 lines
2 KiB
C
83 lines
2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/pci.h>
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#include <fsp/memmap.h>
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#include <intelblocks/smm.h>
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#include <soc/systemagent.h>
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#include <soc/pci_devs.h>
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#include "chip.h"
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void *cbmem_top(void)
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{
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const struct device *dev;
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const config_t *config;
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void *tolum = (void *)sa_get_tseg_base();
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if (!CONFIG(SOC_INTEL_GLK))
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return tolum;
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dev = pcidev_path_on_root(PCH_DEVFN_LPC);
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assert(dev != NULL);
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config = dev->chip_info;
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if (!config)
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die_with_post_code(POST_HW_INIT_FAILURE,
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"Failed to get chip_info\n");
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/* FSP allocates 2x PRMRR Size Memory for alignment */
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if (config->sgx_enable)
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tolum -= config->PrmrrSize * 2;
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return tolum;
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}
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int smm_subregion(int sub, void **start, size_t *size)
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{
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uintptr_t sub_base;
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size_t sub_size;
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void *smm_base;
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const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
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smm_region_info(&smm_base, &sub_size);
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sub_base = (uintptr_t)smm_base;
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assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
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switch (sub) {
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case SMM_SUBREGION_HANDLER:
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/* Handler starts at the base of TSEG. */
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sub_size -= cache_size;
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break;
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case SMM_SUBREGION_CACHE:
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/* External cache is in the middle of TSEG. */
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sub_base += sub_size - cache_size;
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sub_size = cache_size;
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break;
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default:
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return -1;
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}
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*start = (void *)sub_base;
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*size = sub_size;
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return 0;
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}
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