168 lines
3.9 KiB
Plaintext
168 lines
3.9 KiB
Plaintext
# Sample config file for
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# the Iwill DK8X
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# This will make a target directory of ./dk8x
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target dk8x
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mainboard iwill/dk8x
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option HAVE_HARD_RESET=1
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option HAVE_OPTION_TABLE=1
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option HAVE_MP_TABLE=1
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option ROM_SIZE=1024*1024
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option HAVE_FALLBACK_BOOT=1
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#option CONFIG_LSI_SCSI_FW_FIXUP=1
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#
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###
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### Build code to export a programmable irq routing table
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###
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option HAVE_PIRQ_TABLE=1
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option IRQ_SLOT_COUNT=12
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#
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###
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### Build code for SMP support
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### Only worry about 2 micro processors
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###
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option CONFIG_SMP=1
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option CONFIG_MAX_CPUS=2
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#option CONFIG_LOGICAL_CPUS=1
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option CONFIG_MAX_PHYSICAL_CPUS=2
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#
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###
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### Build code to setup a generic IOAPIC
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###
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option CONFIG_IOAPIC=1
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#
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###
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### MEMORY_HOLE instructs earlymtrr.inc to
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### enable caching from 0-640KB and to disable
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### caching from 640KB-1MB using fixed MTRRs
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###
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### Enabling this option breaks SMP because secondary
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### CPU identification depends on only variable MTRRs
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### being enabled.
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###
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#option MEMORY_HOLE=0
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#
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###
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### Clean up the motherboard id strings
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###
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option MAINBOARD_PART_NUMBER="DK8X"
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option MAINBOARD_VENDOR="IWILL"
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#
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###
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### Compute the location and size of where this firmware image
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### (coreboot plus bootloader) will live in the boot rom chip.
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###
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#option FALLBACK_SIZE=524288
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#option FALLBACK_SIZE=98304
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option FALLBACK_SIZE=131072
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## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
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option ROM_IMAGE_SIZE=65536
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###
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### Compute where this copy of coreboot will start in the boot rom
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###
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#
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###
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## We do use compressed image
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#option CONFIG_COMPRESS=1
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option CONFIG_CONSOLE_SERIAL8250=1
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option TTYS0_BAUD=115200
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##
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### Select the coreboot loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## Request this level of debugging output
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option DEFAULT_CONSOLE_LOGLEVEL=7
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## At a maximum only compile in this level of debugging
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option MAXIMUM_CONSOLE_LOGLEVEL=7
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#option DEBUG=1
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#
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## Coreboot C code runs at this location in RAM
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option _RAMBASE=0x004000
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##
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## Use a 32K stack
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##
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option STACK_SIZE=0x8000
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##
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## Use a 56K heap
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##
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option HEAP_SIZE=0xe000
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#
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###
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### Compute the start location and size size of
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### The coreboot bootloader.
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###
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option CONFIG_ROM_PAYLOAD = 1
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#
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#
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romimage "normal"
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# 48K for SCSI FW
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# option ROM_SIZE = 512*1024-48*1024
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# 48K for SCSI FW and 48K for ATI ROM
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# option ROM_SIZE = 512*1024-48*1024-48*1024
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option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
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option USE_FALLBACK_IMAGE=0
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option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
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option ROM_SECTION_OFFSET= 0
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option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
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# option XIP_ROM_SIZE = FALLBACK_SIZE
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option XIP_ROM_SIZE = 65536
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option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
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payload /usr/src/filo-0.4.1_btext/filo.elf
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# payload /usr/src/filo-0.4.2/filo.elf
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end
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romimage "fallback"
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option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
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option USE_FALLBACK_IMAGE=1
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option ROM_SECTION_SIZE = FALLBACK_SIZE
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option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
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option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
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# option XIP_ROM_SIZE = FALLBACK_SIZE
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option XIP_ROM_SIZE = 65536
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option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
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payload ../../../payloads/filo.elf
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# payload /usr/src/filo-0.4.2/filo.elf
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end
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buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
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