410 lines
11 KiB
C
410 lines
11 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
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* Copyright (C) 2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* Contains the generic SPI framework
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*/
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#include <stdio.h>
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#include <pci/pci.h>
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#include <stdint.h>
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#include <string.h>
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#include "flash.h"
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#include "spi.h"
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void spi_prettyprint_status_register(struct flashchip *flash);
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int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
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{
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switch (flashbus) {
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case BUS_TYPE_IT87XX_SPI:
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return it8716f_spi_command(writecnt, readcnt, writearr, readarr);
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case BUS_TYPE_ICH7_SPI:
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case BUS_TYPE_ICH9_SPI:
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case BUS_TYPE_VIA_SPI:
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return ich_spi_command(writecnt, readcnt, writearr, readarr);
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default:
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printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
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}
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return 1;
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}
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static int spi_rdid(unsigned char *readarr, int bytes)
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{
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const unsigned char cmd[JEDEC_RDID_OUTSIZE] = {JEDEC_RDID};
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if (spi_command(sizeof(cmd), bytes, cmd, readarr))
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return 1;
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printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], readarr[2]);
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return 0;
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}
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static int spi_res(unsigned char *readarr)
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{
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const unsigned char cmd[JEDEC_RES_OUTSIZE] = {JEDEC_RES, 0, 0, 0};
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if (spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr))
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return 1;
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printf_debug("RES returned %02x.\n", readarr[0]);
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return 0;
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}
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void spi_write_enable()
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{
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const unsigned char cmd[JEDEC_WREN_OUTSIZE] = {JEDEC_WREN};
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/* Send WREN (Write Enable) */
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spi_command(sizeof(cmd), 0, cmd, NULL);
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}
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void spi_write_disable()
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{
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const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = {JEDEC_WRDI};
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/* Send WRDI (Write Disable) */
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spi_command(sizeof(cmd), 0, cmd, NULL);
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}
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static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
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{
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unsigned char readarr[4];
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uint32_t manuf_id;
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uint32_t model_id;
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if (spi_rdid(readarr, bytes))
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return 0;
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if (!oddparity(readarr[0]))
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printf_debug("RDID byte 0 parity violation.\n");
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/* Check if this is a continuation vendor ID */
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if (readarr[0] == 0x7f) {
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if (!oddparity(readarr[1]))
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printf_debug("RDID byte 1 parity violation.\n");
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manuf_id = (readarr[0] << 8) | readarr[1];
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model_id = readarr[2];
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if (bytes > 3) {
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model_id <<= 8;
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model_id |= readarr[3];
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}
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} else {
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manuf_id = readarr[0];
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model_id = (readarr[1] << 8) | readarr[2];
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}
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printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id);
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if (manuf_id == flash->manufacture_id &&
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model_id == flash->model_id) {
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/* Print the status register to tell the
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* user about possible write protection.
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*/
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spi_prettyprint_status_register(flash);
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return 1;
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}
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/* Test if this is a pure vendor match. */
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if (manuf_id == flash->manufacture_id &&
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GENERIC_DEVICE_ID == flash->model_id)
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return 1;
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return 0;
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}
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int probe_spi_rdid(struct flashchip *flash) {
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return probe_spi_rdid_generic(flash, 3);
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}
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/* support 4 bytes flash ID */
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int probe_spi_rdid4(struct flashchip *flash) {
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/* only some SPI chipsets support 4 bytes commands */
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switch (flashbus) {
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case BUS_TYPE_ICH7_SPI:
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case BUS_TYPE_ICH9_SPI:
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case BUS_TYPE_VIA_SPI:
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return probe_spi_rdid_generic(flash, 4);
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default:
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printf_debug("4b ID not supported on this SPI controller\n");
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}
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return 0;
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}
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int probe_spi_res(struct flashchip *flash)
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{
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unsigned char readarr[3];
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uint32_t model_id;
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if (spi_rdid(readarr, 3))
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/* We couldn't issue RDID, it's pointless to try RES. */
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return 0;
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/* Check if RDID returns 0xff 0xff 0xff, then we use RES. */
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if ((readarr[0] != 0xff) || (readarr[1] != 0xff) ||
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(readarr[2] != 0xff))
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return 0;
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if (spi_res(readarr))
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return 0;
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model_id = readarr[0];
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printf_debug("%s: id 0x%x\n", __FUNCTION__, model_id);
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if (model_id != flash->model_id)
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return 0;
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/* Print the status register to tell the
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* user about possible write protection.
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*/
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spi_prettyprint_status_register(flash);
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return 1;
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}
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uint8_t spi_read_status_register()
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{
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const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = {JEDEC_RDSR};
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unsigned char readarr[JEDEC_RDSR_INSIZE];
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/* Read Status Register */
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spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
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return readarr[0];
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}
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/* Prettyprint the status register. Common definitions.
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*/
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void spi_prettyprint_status_register_common(uint8_t status)
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{
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printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
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"%sset\n", (status & (1 << 5)) ? "" : "not ");
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printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is "
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"%sset\n", (status & (1 << 4)) ? "" : "not ");
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printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
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"%sset\n", (status & (1 << 3)) ? "" : "not ");
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printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
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"%sset\n", (status & (1 << 2)) ? "" : "not ");
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printf_debug("Chip status register: Write Enable Latch (WEL) is "
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"%sset\n", (status & (1 << 1)) ? "" : "not ");
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printf_debug("Chip status register: Write In Progress (WIP/BUSY) is "
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"%sset\n", (status & (1 << 0)) ? "" : "not ");
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}
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/* Prettyprint the status register. Works for
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* ST M25P series
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* MX MX25L series
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*/
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void spi_prettyprint_status_register_st_m25p(uint8_t status)
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{
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printf_debug("Chip status register: Status Register Write Disable "
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"(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
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printf_debug("Chip status register: Bit 6 is "
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"%sset\n", (status & (1 << 6)) ? "" : "not ");
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spi_prettyprint_status_register_common(status);
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}
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/* Prettyprint the status register. Works for
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* SST 25VF016
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*/
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void spi_prettyprint_status_register_sst25vf016(uint8_t status)
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{
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const char *bpt[] = {
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"none",
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"1F0000H-1FFFFFH",
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"1E0000H-1FFFFFH",
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"1C0000H-1FFFFFH",
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"180000H-1FFFFFH",
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"100000H-1FFFFFH",
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"all", "all"
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};
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printf_debug("Chip status register: Block Protect Write Disable "
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"(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
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printf_debug("Chip status register: Auto Address Increment Programming "
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"(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
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spi_prettyprint_status_register_common(status);
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printf_debug("Resulting block protection : %s\n",
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bpt[(status & 0x1c) >> 2]);
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}
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void spi_prettyprint_status_register(struct flashchip *flash)
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{
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uint8_t status;
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status = spi_read_status_register();
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printf_debug("Chip status register is %02x\n", status);
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switch (flash->manufacture_id) {
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case ST_ID:
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if (((flash->model_id & 0xff00) == 0x2000) ||
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((flash->model_id & 0xff00) == 0x2500))
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spi_prettyprint_status_register_st_m25p(status);
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break;
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case MX_ID:
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if ((flash->model_id & 0xff00) == 0x2000)
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spi_prettyprint_status_register_st_m25p(status);
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break;
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case SST_ID:
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if (flash->model_id == SST_25VF016B)
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spi_prettyprint_status_register_sst25vf016(status);
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break;
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}
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}
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int spi_chip_erase_c7(struct flashchip *flash)
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{
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const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = {JEDEC_CE_C7};
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spi_disable_blockprotect();
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spi_write_enable();
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/* Send CE (Chip Erase) */
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spi_command(sizeof(cmd), 0, cmd, NULL);
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/* Wait until the Write-In-Progress bit is cleared.
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* This usually takes 1-85 s, so wait in 1 s steps.
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*/
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while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
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sleep(1);
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return 0;
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}
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/* Block size is usually
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* 64k for Macronix
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* 32k for SST
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* 4-32k non-uniform for EON
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*/
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int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr)
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{
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unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = {JEDEC_BE_D8};
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cmd[1] = (addr & 0x00ff0000) >> 16;
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cmd[2] = (addr & 0x0000ff00) >> 8;
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cmd[3] = (addr & 0x000000ff);
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spi_write_enable();
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/* Send BE (Block Erase) */
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spi_command(sizeof(cmd), 0, cmd, NULL);
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/* Wait until the Write-In-Progress bit is cleared.
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* This usually takes 100-4000 ms, so wait in 100 ms steps.
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*/
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while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
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usleep(100 * 1000);
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return 0;
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}
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/* Sector size is usually 4k, though Macronix eliteflash has 64k */
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int spi_sector_erase(const struct flashchip *flash, unsigned long addr)
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{
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unsigned char cmd[JEDEC_SE_OUTSIZE] = {JEDEC_SE};
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cmd[1] = (addr & 0x00ff0000) >> 16;
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cmd[2] = (addr & 0x0000ff00) >> 8;
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cmd[3] = (addr & 0x000000ff);
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spi_write_enable();
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/* Send SE (Sector Erase) */
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spi_command(sizeof(cmd), 0, cmd, NULL);
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/* Wait until the Write-In-Progress bit is cleared.
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* This usually takes 15-800 ms, so wait in 10 ms steps.
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*/
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while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
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usleep(10 * 1000);
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return 0;
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}
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/*
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* This is according the SST25VF016 datasheet, who knows it is more
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* generic that this...
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*/
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void spi_write_status_register(int status)
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{
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const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = {JEDEC_WRSR, (unsigned char)status};
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/* Send WRSR (Write Status Register) */
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spi_command(sizeof(cmd), 0, cmd, NULL);
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}
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void spi_byte_program(int address, uint8_t byte)
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{
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const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = {JEDEC_BYTE_PROGRAM,
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(address>>16)&0xff,
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(address>>8)&0xff,
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(address>>0)&0xff,
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byte
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};
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/* Send Byte-Program */
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spi_command(sizeof(cmd), 0, cmd, NULL);
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}
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void spi_disable_blockprotect(void)
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{
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uint8_t status;
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status = spi_read_status_register();
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/* If there is block protection in effect, unprotect it first. */
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if ((status & 0x3c) != 0) {
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printf_debug("Some block protection in effect, disabling\n");
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spi_write_enable();
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spi_write_status_register(status & ~0x3c);
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}
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}
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void spi_nbyte_read(int address, uint8_t *bytes, int len)
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{
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const unsigned char cmd[JEDEC_READ_OUTSIZE] = {JEDEC_READ,
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(address >> 16) & 0xff,
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(address >> 8) & 0xff,
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(address >> 0) & 0xff,
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};
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/* Send Read */
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spi_command(sizeof(cmd), len, cmd, bytes);
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}
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int spi_chip_read(struct flashchip *flash, uint8_t *buf)
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{
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switch (flashbus) {
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case BUS_TYPE_IT87XX_SPI:
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return it8716f_spi_chip_read(flash, buf);
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case BUS_TYPE_ICH7_SPI:
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case BUS_TYPE_ICH9_SPI:
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case BUS_TYPE_VIA_SPI:
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return ich_spi_read(flash, buf);
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default:
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printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
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}
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return 1;
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}
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int spi_chip_write(struct flashchip *flash, uint8_t *buf)
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{
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switch (flashbus) {
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case BUS_TYPE_IT87XX_SPI:
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return it8716f_spi_chip_write(flash, buf);
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case BUS_TYPE_ICH7_SPI:
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case BUS_TYPE_ICH9_SPI:
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case BUS_TYPE_VIA_SPI:
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return ich_spi_write(flash, buf);
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default:
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printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
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}
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return 1;
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}
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