326 lines
7.6 KiB
C
326 lines
7.6 KiB
C
/* inteltool - dump all registers on an Intel CPU + chipset based system */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdio.h>
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#include <stdlib.h>
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#include "inteltool.h"
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#define RCBA16(rcba, x) (*((volatile u16 *)((rcba) + (x))))
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#define RCBA32(rcba, x) (*((volatile u32 *)((rcba) + (x))))
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/* IO Buffer Programming */
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#define IOBPIRI 0x2330
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#define IOBPD 0x2334
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#define IOBPS 0x2338
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#define IOBPS_READY 0x0001
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#define IOBPS_TX_MASK 0x0006
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#define IOBPS_MASK 0xff00
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#define IOBPS_READ 0x0600
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#define IOBPS_WRITE 0x0700
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#define IOBPU 0x233a
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#define IOBPU_MAGIC 0xf000
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#define IOBP_RETRY 1000
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static inline int iobp_poll(volatile uint8_t *rcba)
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{
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for (int try = IOBP_RETRY; try > 0; try--) {
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u16 status = RCBA16(rcba, IOBPS);
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if ((status & IOBPS_READY) == 0)
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return 1;
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// udelay(10);
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}
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printf("IOBP: timeout waiting for transaction to complete\n");
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return 0;
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}
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static u32 pch_iobp_read(volatile uint8_t *rcba, u32 address)
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{
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u16 status;
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if (!iobp_poll(rcba))
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return 0;
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/* Set the address */
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RCBA32(rcba, IOBPIRI) = address;
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/* READ OPCODE */
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status = RCBA16(rcba, IOBPS);
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status &= ~IOBPS_MASK;
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status |= IOBPS_READ;
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RCBA16(rcba, IOBPS) = status;
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/* Undocumented magic */
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RCBA16(rcba, IOBPU) = IOBPU_MAGIC;
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/* Set ready bit */
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status = RCBA16(rcba, IOBPS);
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status |= IOBPS_READY;
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RCBA16(rcba, IOBPS) = status;
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if (!iobp_poll(rcba))
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return 0;
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/* Check for successful transaction */
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status = RCBA16(rcba, IOBPS);
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if (status & IOBPS_TX_MASK) {
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printf("IOBP: read 0x%08x failed\n", address);
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return 0;
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}
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/* Read IOBP data */
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return RCBA32(rcba, IOBPD);
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}
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struct iobp_register {
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u32 addr;
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const char *name;
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};
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static const struct iobp_register lynxpoint_iobp_registers[] = {
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/* SATA Electrical Control Register */
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{0xea002488, "SECRT88P0"},
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{0xea00248c, "SECRT8CP0"},
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{0xea002490, "SECRT90P0"},
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{0xea002498, "SECRT98P0"},
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{0xea00251c, "SECRR1CP0"},
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{0xea002550, "SECRR50P0"},
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{0xea002554, "SECRR54P0"},
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{0xea002558, "SECRR58P0"},
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{0xea002688, "SECRT88P1"},
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{0xea00268c, "SECRT8CP1"},
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{0xea002690, "SECRT90P1"},
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{0xea002698, "SECRT98P1"},
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{0xea00271c, "SECRR1CP1"},
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{0xea002750, "SECRR50P1"},
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{0xea002754, "SECRR54P1"},
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{0xea002758, "SECRR58P1"},
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{0xea000888, "SECRT88P2"},
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{0xea00088c, "SECRT8CP2"},
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{0xea000890, "SECRT90P2"},
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{0xea000898, "SECRT98P2"},
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{0xea00091c, "SECRR1CP2"},
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{0xea000950, "SECRR50P2"},
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{0xea000954, "SECRR54P2"},
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{0xea000958, "SECRR58P2"},
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{0xea000a88, "SECRT88P3"},
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{0xea000a8c, "SECRT8CP3"},
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{0xea000a90, "SECRT90P3"},
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{0xea000a98, "SECRT98P3"},
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{0xea000b1c, "SECRR1CP3"},
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{0xea000b50, "SECRR50P3"},
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{0xea000b54, "SECRR54P3"},
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{0xea000b58, "SECRR58P3"},
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{0xea002088, "SECRT88P4"},
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{0xea00208c, "SECRT8CP4"},
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{0xea002090, "SECRT90P4"},
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{0xea002098, "SECRT98P4"},
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{0xea00211c, "SECRR1CP4"},
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{0xea002150, "SECRR50P4"},
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{0xea002154, "SECRR54P4"},
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{0xea002158, "SECRR58P4"},
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{0xea002288, "SECRT88P5"},
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{0xea00228c, "SECRT8CP5"},
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{0xea002290, "SECRT90P5"},
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{0xea002298, "SECRT98P5"},
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{0xea00231c, "SECRR1CP5"},
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{0xea002350, "SECRR50P5"},
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{0xea002354, "SECRR54P5"},
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{0xea002358, "SECRR58P5"},
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{0xea008100, "SECRF00"},
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{0xea008104, "SECRF04"},
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/* USB 2.0 Electrical Control Register */
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{0xe5004100, "U2ECRP01"},
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{0xe5004200, "U2ECRP02"},
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{0xe5004300, "U2ECRP03"},
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{0xe5004400, "U2ECRP04"},
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{0xe5004500, "U2ECRP05"},
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{0xe5004600, "U2ECRP06"},
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{0xe5004700, "U2ECRP07"},
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{0xe5004800, "U2ECRP08"},
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{0xe5004900, "U2ECRP09"},
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{0xe5004a00, "U2ECRP10"},
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{0xe5004b00, "U2ECRP11"},
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{0xe5004c00, "U2ECRP12"},
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{0xe5004d00, "U2ECRP13"},
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{0xe5004e00, "U2ECRP14"},
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/* IOBP related to USB 3.0 ports */
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/* port 1 */
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{0xe900175c, ""},
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{0xe9001760, ""},
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{0xe9001768, ""},
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{0xe9001770, ""},
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{0xe90017cc, ""},
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/* port 2 */
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{0xe900155c, ""},
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{0xe9001560, ""},
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{0xe9001568, ""},
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{0xe9001570, ""},
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{0xe90015cc, ""},
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/* port 3 */
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{0xe9002f5c, ""},
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{0xe9002f60, ""},
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{0xe9002f68, ""},
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{0xe9002f70, ""},
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{0xe9002fcc, ""},
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/* port 4 */
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{0xe9002d5c, ""},
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{0xe9002d60, ""},
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{0xe9002d68, ""},
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{0xe9002d70, ""},
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{0xe9002dcc, ""},
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/* port 5 */
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{0xe900335c, ""},
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{0xe9003360, ""},
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{0xe9003368, ""},
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{0xe9003370, ""},
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{0xe90033cc, ""},
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/* port 6 */
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{0xe900315c, ""},
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{0xe9003160, ""},
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{0xe9003168, ""},
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{0xe9003170, ""},
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{0xe90031cc, ""},
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};
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static const struct iobp_register lynxpoint_lp_iobp_registers[] = {
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/* SATA Electrical Control Register */
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{0xea002688, "SECRT88P0"},
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{0xea00268c, "SECRT8CP0"},
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{0xea002690, "SECRT90P0"},
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{0xea002698, "SECRT98P0"},
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{0xea00271c, "SECRR1CP0"},
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{0xea002750, "SECRR50P0"},
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{0xea002754, "SECRR54P0"},
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{0xea002758, "SECRR58P0"},
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{0xea002488, "SECRT88P1"},
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{0xea00248c, "SECRT8CP1"},
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{0xea002490, "SECRT90P1"},
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{0xea002498, "SECRT98P1"},
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{0xea00251c, "SECRR1CP1"},
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{0xea002550, "SECRR50P1"},
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{0xea002554, "SECRR54P1"},
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{0xea002558, "SECRR58P1"},
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{0xea002288, "SECRT88P2"},
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{0xea00228c, "SECRT8CP2"},
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{0xea002290, "SECRT90P2"},
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{0xea002298, "SECRT98P2"},
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{0xea00231c, "SECRR1CP2"},
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{0xea002350, "SECRR50P2"},
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{0xea002354, "SECRR54P2"},
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{0xea002358, "SECRR58P2"},
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{0xea002088, "SECRT88P3"},
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{0xea00208c, "SECRT8CP3"},
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{0xea002090, "SECRT90P3"},
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{0xea002098, "SECRT98P3"},
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{0xea00211c, "SECRR1CP3"},
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{0xea002150, "SECRR50P3"},
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{0xea002154, "SECRR54P3"},
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{0xea002158, "SECRR58P3"},
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{0xea008100, "SECRF00"},
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{0xea008104, "SECRF04"},
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/* USB 2.0 Electrical Control Register, 8 for -U SoC and 10 for Core-M */
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{0xe5004100, "U2ECRP01"},
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{0xe5004200, "U2ECRP02"},
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{0xe5004300, "U2ECRP03"},
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{0xe5004400, "U2ECRP04"},
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{0xe5004500, "U2ECRP05"},
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{0xe5004600, "U2ECRP06"},
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{0xe5004700, "U2ECRP07"},
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{0xe5004800, "U2ECRP08"},
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{0xe5004900, "U2ECRP09"},
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{0xe5004a00, "U2ECRP10"},
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/* IOBP related to USB 3.0 ports */
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/* port 1 */
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{0xe900215c, ""},
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{0xe9002160, ""},
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{0xe9002168, ""},
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{0xe9002170, ""},
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{0xe90021cc, ""},
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/* port 2 */
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{0xe900235c, ""},
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{0xe9002360, ""},
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{0xe9002368, ""},
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{0xe9002370, ""},
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{0xe90023cc, ""},
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/* port 3 */
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{0xe900255c, ""},
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{0xe9002560, ""},
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{0xe9002568, ""},
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{0xe9002570, ""},
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{0xe90025cc, ""},
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/* port 4 */
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{0xe900275c, ""},
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{0xe9002760, ""},
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{0xe9002768, ""},
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{0xe9002770, ""},
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{0xe90027cc, ""},
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};
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void print_iobp(struct pci_dev *sb, volatile uint8_t *rcba)
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{
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const struct iobp_register *iobp_registers = NULL;
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size_t iobp_size = 0;
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_C8_MOBILE:
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case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
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case PCI_DEVICE_ID_INTEL_Z87:
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case PCI_DEVICE_ID_INTEL_Z85:
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case PCI_DEVICE_ID_INTEL_HM86:
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case PCI_DEVICE_ID_INTEL_H87:
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case PCI_DEVICE_ID_INTEL_HM87:
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case PCI_DEVICE_ID_INTEL_Q85:
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case PCI_DEVICE_ID_INTEL_Q87:
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case PCI_DEVICE_ID_INTEL_QM87:
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case PCI_DEVICE_ID_INTEL_B85:
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case PCI_DEVICE_ID_INTEL_C222:
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case PCI_DEVICE_ID_INTEL_C224:
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case PCI_DEVICE_ID_INTEL_C226:
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case PCI_DEVICE_ID_INTEL_H81:
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case PCI_DEVICE_ID_INTEL_C9_MOBILE:
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case PCI_DEVICE_ID_INTEL_C9_DESKTOP:
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case PCI_DEVICE_ID_INTEL_HM97:
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case PCI_DEVICE_ID_INTEL_Z97:
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case PCI_DEVICE_ID_INTEL_H97:
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iobp_registers = lynxpoint_iobp_registers;
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iobp_size = ARRAY_SIZE(lynxpoint_iobp_registers);
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break;
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
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case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
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case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
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iobp_registers = lynxpoint_lp_iobp_registers;
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iobp_size = ARRAY_SIZE(lynxpoint_lp_iobp_registers);
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break;
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default:
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break;
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}
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if (iobp_size == 0)
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return;
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printf("\n============= IOBP ==============\n\n");
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for (size_t i = 0; i < iobp_size; i++) {
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u32 address = iobp_registers[i].addr;
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const char *name = iobp_registers[i].name;
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u32 v = pch_iobp_read(rcba, address);
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printf("0x%08x: 0x%08x (%s)\n", address, v, name);
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}
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}
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