Marc Jones 290a59284e soc/amd/stoneyridge: Add CPU PPKG ASL ... Add PPKG Method for processor passive thermal control list. BUG=b:67999819 Change-Id: I5d84832af06f64c923485926e4e0c73c65a2b0b2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22399 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>		2017-11-13 17:36:51 +00:00
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amd	soc/amd/stoneyridge: Add CPU PPKG ASL	2017-11-13 17:36:51 +00:00
broadcom	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
dmp	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
imgtec	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
intel	soc/intel/apollolake: Make use of Intel SPI common block	2017-11-11 18:20:12 +00:00
lowrisc	RISC-V boards: Stop using the config string	2017-11-07 12:31:00 +00:00
marvell	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
mediatek	soc/mediatek/mt8173: Remove cast of NULL* to void *	2017-11-03 16:03:30 +00:00
nvidia	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
qualcomm	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
rockchip	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
samsung	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
ucb	RISC-V boards: Stop using the config string	2017-11-07 12:31:00 +00:00