a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
104 lines
2.9 KiB
Text
104 lines
2.9 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Global Variables */
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Name(\PICM, 0) // IOAPIC/8259
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/* Global ACPI memory region. This region is used for passing information
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* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
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* Since we don't know where this will end up in memory at ACPI compile time,
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* we have to fix it up in coreboot's ACPI creation phase.
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*/
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External(NVSA)
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OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Miscellaneous */
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Offset (0x00),
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OSYS, 16, // 0x00 - Operating System
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SMIF, 8, // 0x02 - SMI function
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PRM0, 8, // 0x03 - SMI function parameter
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PRM1, 8, // 0x04 - SMI function parameter
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SCIF, 8, // 0x05 - SCI function
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PRM2, 8, // 0x06 - SCI function parameter
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PRM3, 8, // 0x07 - SCI function parameter
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LCKF, 8, // 0x08 - Global Lock function for EC
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PRM4, 8, // 0x09 - Lock function parameter
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PRM5, 8, // 0x0a - Lock function parameter
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P80D, 32, // 0x0b - Debug port (IO 0x80) value
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LIDS, 8, // 0x0f - LID state (open = 1)
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PWRS, 8, // 0x10 - Power State (AC = 1)
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PCNT, 8, // 0x11 - Processor count
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TPMP, 8, // 0x12 - TPM Present and Enabled
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TLVL, 8, // 0x13 - Throttle Level
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PPCM, 8, // 0x14 - Maximum P-state usable by OS
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PM1I, 32, // 0x15 - System Wake Source - PM1 Index
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/* Device Config */
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Offset (0x20),
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S5U0, 8, // 0x20 - Enable USB0 in S5
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S5U1, 8, // 0x21 - Enable USB1 in S5
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S3U0, 8, // 0x22 - Enable USB0 in S3
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S3U1, 8, // 0x23 - Enable USB1 in S3
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TACT, 8, // 0x24 - Thermal Active trip point
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TPSV, 8, // 0x25 - Thermal Passive trip point
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TCRT, 8, // 0x26 - Thermal Critical trip point
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DPTE, 8, // 0x27 - Enable DPTF
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/* Base addresses */
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Offset (0x30),
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CMEM, 32, // 0x30 - CBMEM TOC
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TOLM, 32, // 0x34 - Top of Low Memory
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CBMC, 32, // 0x38 - coreboot mem console pointer
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/* ChromeOS specific */
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Offset (0x100),
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#include <vendorcode/google/chromeos/acpi/gnvs.asl>
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Offset (0x1000),
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#include <soc/intel/baytrail/acpi/device_nvs.asl>
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}
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/* Set flag to enable USB charging in S3 */
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Method (S3UE)
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{
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Store (One, \S3U0)
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Store (One, \S3U1)
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}
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/* Set flag to disable USB charging in S3 */
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Method (S3UD)
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{
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Store (Zero, \S3U0)
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Store (Zero, \S3U1)
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}
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/* Set flag to enable USB charging in S5 */
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Method (S5UE)
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{
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Store (One, \S5U0)
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Store (One, \S5U1)
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}
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/* Set flag to disable USB charging in S5 */
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Method (S5UD)
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{
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Store (Zero, \S5U0)
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Store (Zero, \S5U1)
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}
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