9d0aa99c5e
In preparation to deleting early_setup,c, change early_ec_init() to use new southbridge.c function sb_set_wideio_range and remove <#ifdef __PRE_RAM__>. BUG=b:64033893 TEST=Build, boot and check serial output, search for "Covered by wideIO xx", which should match earlier message "Range assigned to wide IO xx" generated within modified early_ec_init(). Change-Id: Iaea17f4f636aab6bd8b05b1b3bed53a677164e74 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
66 lines
1.8 KiB
C
66 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <console/console.h>
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#include <ec/google/chromeec/ec.h>
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#include <rules.h>
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#include <soc/southbridge.h>
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#include <variant/ec.h>
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static void ramstage_ec_init(void)
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{
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const struct google_chromeec_event_info info = {
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.log_events = MAINBOARD_EC_LOG_EVENTS,
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.sci_events = MAINBOARD_EC_SCI_EVENTS,
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.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
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.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
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};
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printk(BIOS_DEBUG, "mainboard: EC init\n");
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google_chromeec_events_init(&info, acpi_is_wakeup_s3());
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}
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static void early_ec_init(void)
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{
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uint16_t ec_ioport_base;
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size_t ec_ioport_size;
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int status;
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/*
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* Set up LPC decoding for the ChromeEC I/O port ranges:
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* - Ports 62/66, 60/64, and 200->208
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* -- set by hudson_lpc_decode() in pre
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* - ChromeEC specific communication I/O ports.
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*/
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google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
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printk(BIOS_DEBUG,
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"LPC Setup google_chromeec_ioport_range: %04x, %08zx\n",
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ec_ioport_base, ec_ioport_size);
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status = sb_set_wideio_range(ec_ioport_base, ec_ioport_size);
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if (status == WIDEIO_RANGE_ERROR)
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printk(BIOS_WARNING, "ERROR: Failed to assign a range\n");
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else
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printk(BIOS_DEBUG, "Range assigned to wide IO %d\n", status);
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}
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void mainboard_ec_init(void)
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{
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if (ENV_RAMSTAGE)
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ramstage_ec_init();
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else
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early_ec_init();
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}
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