coreboot-kgpe-d16/src/soc
Martin Roth f812c44f00 intel/braswell: Build in both C0 and 'other' vbios
The Braswell CPU seems to have two different Video BIOS roms, one for
the C0 revision, and one for other revisions.  Build them both into
the coreboot image, and let coreboot sort out which one should be used
at runtime.  This should allow one rom to be used for all revisions.

The initial reason for this patch was that the Kconfig symbol
C0_DISP_SUPPORT didn't exist, and was causing issues.  This
seems like the best way to eliminate the need for that symbol.

Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12826
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06 17:41:49 +01:00
..
broadcom/cygnus arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00
imgtec/pistachio imgtec/pistachio: disable default RPU gate register values 2015-12-31 17:36:06 +01:00
intel intel/braswell: Build in both C0 and 'other' vbios 2016-01-06 17:41:49 +01:00
marvell/bg4cd arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00
mediatek/mt8173 soc/mediatek/mt8173: SPI_ATOMIC_SEQUENCING depends on SPI_FLASH 2015-12-10 16:37:05 +01:00
nvidia arm64: tegra132: tegra210: Remove old arm64/stage_entry.S 2015-11-17 21:31:20 +01:00
qualcomm/ipq806x cbfs_spi: enable CBFS access in early romstage 2015-12-03 14:17:04 +01:00
rockchip/rk3288 google/veyron*: Pulse the i2c clock once if sda was low 2015-11-18 16:29:16 +01:00
samsung soc/samsung/exynos5250: Implement hard_reset() 2015-12-16 00:41:03 +01:00
ucb/riscv tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00