ee65079c96
Change-Id: Id51da519582856b1856479b641599e14f79fd1ad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
181 lines
5.9 KiB
C
181 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <Porting.h>
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#include <AGESA.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <PlatformMemoryConfiguration.h>
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/*
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* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
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*
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* Lane Id
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* 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
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* 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
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* 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
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* 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
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* 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
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* 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
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* 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
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* 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
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* 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
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* 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
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* 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
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* 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
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* 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
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* 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
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* 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
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* 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
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* 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
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* 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
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* 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
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* 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
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* 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
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* 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
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* 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
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* 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
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* 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
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* 25 DP0_TX[P,N]1
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* 26 DP0_TX[P,N]2
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* 27 DP0_TX[P,N]3
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* 28 DP1_TX[P,N]0
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* 29 DP1_TX[P,N]1
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* 30 DP1_TX[P,N]2
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* 31 DP1_TX[P,N]3
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* 32 DP2_TX[P,N]0
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* 33 DP2_TX[P,N]1
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* 34 DP2_TX[P,N]2
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* 35 DP2_TX[P,N]3
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* 36 DP2_TX[P,N]4
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* 37 DP2_TX[P,N]5
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* 38 DP2_TX[P,N]6
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*/
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static const PCIe_PORT_DESCRIPTOR PortList[] = {
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/* PCIe port, Lanes 8:23, PCI Device Number 2, x16 slot */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 1)
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},
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/* PCIe port, Lane 4, PCI Device Number 4, Realtek LAN */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 1)
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},
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/* PCIe port, Lane 5, PCI Device Number 5, x1 slot (1) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 1)
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},
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/* PCIe port, Lane 6, PCI Device Number 6, x1 slot (2) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 1)
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},
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/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0)
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},
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};
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static const PCIe_DDI_DESCRIPTOR DdiList[] = {
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// DP0 to HDMI0/DP
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
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},
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// DP1 to FCH
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
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},
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// DP2 to HDMI1/DP
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
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},
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};
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.SocketId = 0,
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.PciePortList = PortList,
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.DdiLinkList = DdiList,
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};
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void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
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{
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FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
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FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
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FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE);
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}
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void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
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{
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InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
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}
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/*----------------------------------------------------------------------------------------
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* CUSTOMER OVERRIDES MEMORY TABLE
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*----------------------------------------------------------------------------------------
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*/
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/*
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* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
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* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
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* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
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* use its default conservative settings.
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*/
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static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
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NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
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NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
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/*
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TODO: is this OK for DDR3 socket FM2?
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MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
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CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
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ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
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CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
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*/
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PSO_END
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};
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void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
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{
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InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
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}
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void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
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{
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/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
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InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
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}
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