5b672d5954
Using proper symbols for base addresses, it is possible to only define the symbols for base addresses implemented for the specific platform and executing stage. Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
171 lines
4.9 KiB
C
171 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <AGESA.h>
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#include <amdlib.h>
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#include <amdblocks/acpimmio.h>
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include <SB800.h>
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#include <southbridge/amd/cimx/sb800/gpio_oem.h>
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static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
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static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD, agesa_ReadSpd },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset },
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{AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit },
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{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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/* Call the host environment interface to provide a user hook opportunity. */
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static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status;
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UINTN FcnData;
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MEM_DATA_STRUCT *MemData;
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UINT32 GpioMmioAddr;
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UINT8 Data8;
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UINT8 TempData8;
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FcnData = Data;
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MemData = ConfigPtr;
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Status = AGESA_SUCCESS;
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GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
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Data8 &= ~BIT5;
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TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
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TempData8 &= 0x03;
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TempData8 |= Data8;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
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Data8 |= BIT2+BIT3;
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Data8 &= ~BIT4;
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TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
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TempData8 &= 0x23;
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TempData8 |= Data8;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
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Data8 &= ~BIT5;
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TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
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TempData8 &= 0x03;
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TempData8 |= Data8;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
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Data8 |= BIT2+BIT3;
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Data8 &= ~BIT4;
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TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
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TempData8 &= 0x23;
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TempData8 |= Data8;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
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switch (MemData->ParameterListPtr->DDR3Voltage) {
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case VOLT1_35:
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
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Data8 |= (UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
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break;
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case VOLT1_25:
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
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break;
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case VOLT1_5:
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default:
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
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Data8 |= (UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
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}
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return Status;
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}
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/* PCIE slot reset control */
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static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status;
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UINTN FcnData;
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PCIe_SLOT_RESET_INFO *ResetInfo;
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UINT32 GpioMmioAddr;
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UINT8 Data8;
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GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
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FcnData = Data;
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ResetInfo = ConfigPtr;
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Status = AGESA_UNSUPPORTED;
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switch (ResetInfo->ResetId) {
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case 4:
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switch (ResetInfo->ResetControl) {
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case AssertSlotReset:
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
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Data8 &= ~(UINT8)BIT6;
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/* MXM_GPIO0. GPIO21 */
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
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Status = AGESA_SUCCESS;
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break;
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case DeassertSlotReset:
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
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Data8 |= BIT6;
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/* MXM_GPIO0. GPIO21 */
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
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Status = AGESA_SUCCESS;
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break;
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}
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break;
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case 6:
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switch (ResetInfo->ResetControl) {
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case AssertSlotReset:
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
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Data8 &= ~(UINT8)BIT6;
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/* PCIE_RST#_LAN, GPIO25 */
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
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Status = AGESA_SUCCESS;
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break;
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case DeassertSlotReset:
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
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Data8 |= BIT6;
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/* PCIE_RST#_LAN, GPIO25 */
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
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Status = AGESA_SUCCESS;
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break;
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}
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break;
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case 7:
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switch (ResetInfo->ResetControl) {
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case AssertSlotReset:
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
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Data8 &= ~(UINT8)BIT6;
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/* MPCIE_RST0, GPIO02 */
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
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Status = AGESA_SUCCESS;
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break;
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case DeassertSlotReset:
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
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Data8 |= BIT6;
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/* MPCIE_RST0, GPIO02 */
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
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Status = AGESA_SUCCESS;
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break;
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}
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break;
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}
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return Status;
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}
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