2c18ba5bd7
SATA Mode Select is bit 16 of the SATA General Configuration register. This code currently incorrectly pokes at the Port Clock Disable bits in the Port Mapping Register, and without clock the affected ports can't link. Change-Id: I37104f520a869bd45a32cfd271d0b893aec3c8ed Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com> Reviewed-by: David Guckian Reviewed-by: Patrick Georgi <pgeorgi@google.com>
84 lines
2.2 KiB
C
84 lines
2.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 - 2009 coresystems GmbH
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* Copyright (C) 2014 - 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/sata.h>
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#include "chip.h"
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static void sata_init(struct device *dev)
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{
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u32 reg32;
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u32 abar;
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printk(BIOS_DEBUG, "SATA: Initializing...\n");
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/* SATA configuration is handled by the FSP */
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/* Enable BARs */
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pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_IO);
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printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
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/* Set the controller mode */
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reg32 = pci_read_config32(dev, SATAGC);
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reg32 &= ~SATAGC_AHCI;
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pci_write_config32(dev, SATAGC, reg32);
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/* Initialize AHCI memory-mapped space */
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abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
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printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
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/* Enable AHCI Mode */
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reg32 = read32((void *)(abar + 0x04));
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reg32 |= (1 << 31);
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write32((void *)(abar + 0x04), reg32);
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}
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static void sata_enable(struct device *dev) { /* TODO */ }
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static struct device_operations sata_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = sata_init,
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.enable = sata_enable,
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.scan_bus = 0,
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.ops_pci = &soc_pci_ops,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1,
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PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2,
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0
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};
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static const struct pci_driver soc_sata __pci_driver = {
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.ops = &sata_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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