coreboot-kgpe-d16/src/drivers/intel/fsp1_0
Alexandru Gagniuc 2c482a969a intel: Do not hardcode the position of mrc.cache
The reason for hardcoding the position of the MRC cache was to satisfy
the alignment to the erase size of the flash chip. Hardcoding is no
longer needed, as we can specify alignment directly. In the long term,
the MRC cache will have to move to FMAP, but for now, we reduce
fragmentation in CBFS.

Note that soc/intel/common hardcoding of mrc.cache is not removed, as
the mrc cache implementation there does not use CBFS to find the cache
region, and needs a hardcoded address.

Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11527
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-07 17:40:32 +00:00
..
cache_as_ram.inc Remove empty lines at end of file 2015-06-08 00:55:07 +02:00
fastboot_cache.c cbfs: new API and better program loading 2015-06-02 14:09:31 +02:00
fsp_util.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
fsp_util.h Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
fsp_values.h Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
hob.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
Kconfig intel: Do not hardcode the position of mrc.cache 2015-09-07 17:40:32 +00:00
Makefile.inc intel: Do not hardcode the position of mrc.cache 2015-09-07 17:40:32 +00:00