38 lines
1.3 KiB
C
38 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <chip.h>
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#include <amdblocks/agesawrapper.h>
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#define DIMMS_PER_CHANNEL 1
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#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH
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#error "Too many DIMM sockets defined for the mainboard"
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#endif
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static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
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DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
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NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_A, 1),
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NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_B, 1),
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NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
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MOTHER_BOARD_LAYERS(LAYERS_6),
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MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00),
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MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x08, 0x04,
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0x00, 0x00, 0x00, 0x00),
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CKE_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00),
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CKE_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x05, 0x0A, 0x00, 0x00),
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ODT_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x00, 0x02, 0x00),
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ODT_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x04, 0x02, 0x08),
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CS_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00),
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CS_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x04, 0x08, 0x00,
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0x00, 0x00, 0x00),
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PSO_END
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};
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void OemPostParams(AMD_POST_PARAMS *PostParams)
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{
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PostParams->MemConfig.PlatformMemoryConfiguration =
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(PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
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PostParams->MemConfig.CfgUmaAbove4G = TRUE;
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}
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