de8c7e39bc
Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> |
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| .. | ||
| Intel | ||
| RFC | ||
| AMD-S3.txt | ||
| CorebootBuildingGuide.tex | ||
| Doxyfile.coreboot | ||
| Doxyfile.coreboot_simple | ||
| Kconfig.tex | ||
| Makefile | ||
| POSTCODES | ||
| abi-data-consumption.txt | ||
| beginverbatim.tex | ||
| cbfs.txt | ||
| codeflow.svg | ||
| coreboot_logo.png | ||
| endverbatim.tex | ||
| gcov.txt | ||
| gerrit_guidelines.md | ||
| hypertransport.svg | ||
| mainboard_io_trap_handler_sample.c | ||
| submodules.txt | ||
| timestamp.md | ||
