377 lines
8.2 KiB
C
377 lines
8.2 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _COREBOOT_TABLES_H
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#define _COREBOOT_TABLES_H
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#include <arch/types.h>
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#include <ipchksum.h>
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struct cbuint64 {
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u32 lo;
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u32 hi;
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};
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struct cb_header {
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u8 signature[4];
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u32 header_bytes;
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u32 header_checksum;
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u32 table_bytes;
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u32 table_checksum;
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u32 table_entries;
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};
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struct cb_record {
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u32 tag;
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u32 size;
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};
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#define CB_TAG_UNUSED 0x0000
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#define CB_TAG_MEMORY 0x0001
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struct cb_memory_range {
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struct cbuint64 start;
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struct cbuint64 size;
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u32 type;
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};
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#define CB_MEM_RAM 1
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#define CB_MEM_RESERVED 2
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#define CB_MEM_ACPI 3
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#define CB_MEM_NVS 4
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#define CB_MEM_UNUSABLE 5
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#define CB_MEM_VENDOR_RSVD 6
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#define CB_MEM_TABLE 16
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struct cb_memory {
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u32 tag;
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u32 size;
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struct cb_memory_range map[0];
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};
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#define CB_TAG_HWRPB 0x0002
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struct cb_hwrpb {
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u32 tag;
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u32 size;
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u64 hwrpb;
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};
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#define CB_TAG_MAINBOARD 0x0003
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struct cb_mainboard {
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u32 tag;
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u32 size;
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u8 vendor_idx;
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u8 part_number_idx;
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u8 strings[0];
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};
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#define CB_TAG_VERSION 0x0004
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#define CB_TAG_EXTRA_VERSION 0x0005
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#define CB_TAG_BUILD 0x0006
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#define CB_TAG_COMPILE_TIME 0x0007
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#define CB_TAG_COMPILE_BY 0x0008
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#define CB_TAG_COMPILE_HOST 0x0009
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#define CB_TAG_COMPILE_DOMAIN 0x000a
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#define CB_TAG_COMPILER 0x000b
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#define CB_TAG_LINKER 0x000c
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#define CB_TAG_ASSEMBLER 0x000d
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struct cb_string {
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u32 tag;
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u32 size;
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u8 string[0];
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};
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#define CB_TAG_SERIAL 0x000f
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struct cb_serial {
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u32 tag;
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u32 size;
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#define CB_SERIAL_TYPE_IO_MAPPED 1
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#define CB_SERIAL_TYPE_MEMORY_MAPPED 2
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u32 type;
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u32 baseaddr;
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u32 baud;
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u32 regwidth;
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/* Crystal or input frequency to the chip containing the UART.
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* Provide the board specific details to allow the payload to
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* initialize the chip containing the UART and make independent
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* decisions as to which dividers to select and their values
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* to eventually arrive at the desired console baud-rate. */
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u32 input_hertz;
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/* UART PCI address: bus, device, function
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* 1 << 31 - Valid bit, PCI UART in use
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* Bus << 20
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* Device << 15
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* Function << 12
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*/
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u32 uart_pci_addr;
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};
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#define CB_TAG_CONSOLE 0x00010
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struct cb_console {
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u32 tag;
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u32 size;
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u16 type;
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};
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#define CB_TAG_CONSOLE_SERIAL8250 0
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#define CB_TAG_CONSOLE_VGA 1 // OBSOLETE
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#define CB_TAG_CONSOLE_BTEXT 2 // OBSOLETE
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#define CB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE
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#define CB_TAG_CONSOLE_SROM 4 // OBSOLETE
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#define CB_TAG_CONSOLE_EHCI 5
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#define CB_TAG_FORWARD 0x00011
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struct cb_forward {
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u32 tag;
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u32 size;
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u64 forward;
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};
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#define CB_TAG_FRAMEBUFFER 0x0012
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struct cb_framebuffer {
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u32 tag;
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u32 size;
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u64 physical_address;
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u32 x_resolution;
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u32 y_resolution;
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u32 bytes_per_line;
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u8 bits_per_pixel;
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u8 red_mask_pos;
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u8 red_mask_size;
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u8 green_mask_pos;
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u8 green_mask_size;
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u8 blue_mask_pos;
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u8 blue_mask_size;
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u8 reserved_mask_pos;
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u8 reserved_mask_size;
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};
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#define CB_TAG_GPIO 0x0013
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#define CB_GPIO_ACTIVE_LOW 0
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#define CB_GPIO_ACTIVE_HIGH 1
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#define CB_GPIO_MAX_NAME_LENGTH 16
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struct cb_gpio {
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u32 port;
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u32 polarity;
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u32 value;
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u8 name[CB_GPIO_MAX_NAME_LENGTH];
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};
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struct cb_gpios {
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u32 tag;
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u32 size;
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u32 count;
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struct cb_gpio gpios[0];
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};
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#define CB_TAG_VDAT 0x0015
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#define CB_TAG_VBNV 0x0019
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#define CB_TAG_VBOOT_HANDOFF 0x0020
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#define CB_TAG_DMA 0x0022
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#define CB_TAG_RAM_OOPS 0x0023
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#define CB_TAG_MTC 0x002b
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#define CB_TAG_VPD 0x002c
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struct lb_range {
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uint32_t tag;
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uint32_t size;
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uint64_t range_start;
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uint32_t range_size;
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};
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#define CB_TAG_TIMESTAMPS 0x0016
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#define CB_TAG_CBMEM_CONSOLE 0x0017
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#define CB_TAG_MRC_CACHE 0x0018
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#define CB_TAG_ACPI_GNVS 0x0024
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#define CB_TAG_WIFI_CALIBRATION 0x0027
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struct cb_cbmem_tab {
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uint32_t tag;
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uint32_t size;
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uint64_t cbmem_tab;
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};
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#define CB_TAG_X86_ROM_MTRR 0x0021
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struct cb_x86_rom_mtrr {
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uint32_t tag;
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uint32_t size;
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/* The variable range MTRR index covering the ROM. If one wants to
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* enable caching the ROM, the variable MTRR needs to be set to
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* write-protect. To disable the caching after enabling set the
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* type to uncacheable. */
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uint32_t index;
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};
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#define CB_TAG_BOARD_ID 0x0025
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#define CB_TAG_RAM_CODE 0x0028
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#define CB_TAG_SKU_ID 0x002d
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struct cb_strapping_id {
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uint32_t tag;
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uint32_t size;
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uint32_t id_code;
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};
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#define CB_TAG_SPI_FLASH 0x0029
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struct cb_spi_flash {
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uint32_t tag;
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uint32_t size;
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uint32_t flash_size;
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uint32_t sector_size;
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uint32_t erase_cmd;
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};
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#define CB_TAG_BOOT_MEDIA_PARAMS 0x0030
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struct cb_boot_media_params {
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uint32_t tag;
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uint32_t size;
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/* offsets are relative to start of boot media */
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uint64_t fmap_offset;
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uint64_t cbfs_offset;
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uint64_t cbfs_size;
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uint64_t boot_media_size;
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};
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#define CB_TAG_TSC_INFO 0x0032
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struct cb_tsc_info {
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uint32_t tag;
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uint32_t size;
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uint32_t freq_khz;
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};
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#define CB_TAG_MAC_ADDRS 0x0033
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struct mac_address {
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uint8_t mac_addr[6];
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uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */
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};
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struct cb_macs {
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uint32_t tag;
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uint32_t size;
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uint32_t count;
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struct mac_address mac_addrs[0];
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};
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#define CB_TAG_SERIALNO 0x002a
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#define CB_MAX_SERIALNO_LENGTH 32
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#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
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struct cb_cmos_option_table {
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u32 tag;
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u32 size;
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u32 header_length;
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};
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#define CB_TAG_OPTION 0x00c9
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#define CB_CMOS_MAX_NAME_LENGTH 32
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struct cb_cmos_entries {
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u32 tag;
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u32 size;
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u32 bit;
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u32 length;
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u32 config;
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u32 config_id;
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u8 name[CB_CMOS_MAX_NAME_LENGTH];
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};
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#define CB_TAG_OPTION_ENUM 0x00ca
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#define CB_CMOS_MAX_TEXT_LENGTH 32
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struct cb_cmos_enums {
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u32 tag;
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u32 size;
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u32 config_id;
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u32 value;
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u8 text[CB_CMOS_MAX_TEXT_LENGTH];
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};
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#define CB_TAG_OPTION_DEFAULTS 0x00cb
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#define CB_CMOS_IMAGE_BUFFER_SIZE 128
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struct cb_cmos_defaults {
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u32 tag;
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u32 size;
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u32 name_length;
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u8 name[CB_CMOS_MAX_NAME_LENGTH];
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u8 default_set[CB_CMOS_IMAGE_BUFFER_SIZE];
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};
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#define CB_TAG_OPTION_CHECKSUM 0x00cc
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#define CB_CHECKSUM_NONE 0
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#define CB_CHECKSUM_PCBIOS 1
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struct cb_cmos_checksum {
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u32 tag;
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u32 size;
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u32 range_start;
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u32 range_end;
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u32 location;
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u32 type;
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};
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/* Helpful inlines */
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static inline u64 cb_unpack64(struct cbuint64 val)
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{
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return (((u64) val.hi) << 32) | val.lo;
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}
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static inline u16 cb_checksum(const void *ptr, unsigned len)
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{
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return ipchksum(ptr, len);
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}
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static inline const char *cb_mb_vendor_string(const struct cb_mainboard *cbm)
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{
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return (char *)(cbm->strings + cbm->vendor_idx);
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}
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static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm)
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{
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return (char *)(cbm->strings + cbm->part_number_idx);
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}
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/* Helpful macros */
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#define MEM_RANGE_COUNT(_rec) \
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(((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
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#define MEM_RANGE_PTR(_rec, _idx) \
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(void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \
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+ (sizeof((_rec)->map[0]) * (_idx)))
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#endif
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