Andrew Bresticker 2e709464b9 libpayload: mips: Set BASE_ADDRESS to 0 ... Now that coreboot has identity-mapped DRAM, use base address 0 (KUSEG) instead of 0x80000000 (KSEG0). BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio. Change-Id: I39845250a1b8cea6e5360efce16770751ffce13d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c1cbc1d7f6873c0be30d4206a2030f3b468acf24 Original-Change-Id: I76d98664f1bca73ae8acc9f545e68de9173c3cab Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246695 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9817 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>		2015-04-21 08:12:22 +02:00
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arm	libpayload: sync arch/arm/cache.c with coreboot	2015-04-17 09:27:42 +02:00
arm64	libpayload arm64: Allow board to define upper address limit on DMA	2015-03-23 13:11:24 +01:00
mips	libpayload: mips: Set BASE_ADDRESS to 0	2015-04-21 08:12:22 +02:00
x86	libpayload: move MRC processing to x86 path and remove ACPI_GNVS duplication	2015-03-20 15:33:47 +01:00
Config.in	libpayload: arch/mips: Add basic MIPS architecture support	2015-03-21 11:07:50 +01:00