coreboot-kgpe-d16/spd/lp5/set-1
Karthikeyan Ramasubramanian f53214677c util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)
ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle
time. Encode tCKMin as per the respective advisories.

BUG=None
TEST=Generate the SPD and ensure that tCKMin is encoded accordingly.
Minimum CAS Latency time is also impacted and is encoded accordingly.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-08 23:46:50 +00:00
..
parts_spd_manifest.generated.txt
spd-1.hex util/spd_tools: Encode SDRAM min cycle time (TCKMinPs) 2022-03-08 23:46:50 +00:00
spd-2.hex util/spd_tools: Encode SDRAM min cycle time (TCKMinPs) 2022-03-08 23:46:50 +00:00
spd-3.hex util/spd_tools: Encode SDRAM min cycle time (TCKMinPs) 2022-03-08 23:46:50 +00:00
spd-empty.hex