coreboot-kgpe-d16/src/mainboard/google/gale/reset.c
Varadarajan Narayanan 6fbc763b81 soc/qualcomm/ipq40xx: Enable crashdump handling
Clear the crash dump cookie set by SBL to indicate that
it is a normal reset.

Inform DDR image of the entrypoint for SDI image to be
preserved in OCIMEM which will be needed during watchdog
resets.

BUG=chrome-os-partner:49249
TEST=DDR image is able to fetch the entry point address
BRANCH=none

Change-Id: I3e6e4a108585bb257e3ad02956c420acbcb2554e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bd726256a5ae89672810b57e1d2a7a9287f60627
Original-Change-Id: Id6e09516209f47c3ea8fa3d8d90440789b395660
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333321
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14679
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10 23:24:08 +02:00

32 lines
986 B
C

/*
*
* This file is part of the coreboot project.
*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <soc/iomap.h>
#include <reset.h>
void hard_reset(void)
{
/*
* At boot time the boot loaders would have set a magic cookie
* here to detect watchdog reset. However, since this is a
* normal reset clear the magic numbers.
*/
write32(TCSR_BOOT_MISC_DETECT, 0);
write32(TCSR_RESET_DEBUG_SW_ENTRY, 0);
write32(GCNT_PSHOLD, 0);
}