Felix Held 2eb3ec7563 soc/amd/cezanne/mca: add and use mca_bank_name[] ... This enables the MCAX checking and BERT entry generation for Cezanne. TEST=When printing all registers of all MCAX banks of core 0 on a google/guybrush device, the registers have values that look correctly and there is no general protection fault, so all MCAX MSRs that could be accessed exist on Cezanne. BUG=b:192997706 Change-Id: Ibe8047ce5bb5e7136a8786693bcced4d2225b1fd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56345 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-07-21 22:38:11 +00:00
..
cezanne	soc/amd/cezanne/mca: add and use mca_bank_name[]	2021-07-21 22:38:11 +00:00
common	soc/amd/cezanne: enable crypto in psp_verstage	2021-07-21 16:53:17 +00:00
picasso	soc/amd/cezanne: enable crypto in psp_verstage	2021-07-21 16:53:17 +00:00
stoneyridge	soc/amd/stoneyridge/mca: implement and use mca_has_expected_bank_count	2021-07-15 17:04:28 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00