aee0796506
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
177 lines
5.8 KiB
C
177 lines
5.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef H3FFEAT_H
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#define H3FFEAT_H
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/*----------------------------------------------------------------------------
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* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
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*
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*----------------------------------------------------------------------------
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*/
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/*-----------------------------------------------------------------------------
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* DEFINITIONS AND MACROS
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*
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*-----------------------------------------------------------------------------
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*/
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#define MAX_NODES 8
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#define MAX_LINKS 8
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#define MAX_PLATFORM_LINKS 64 /* 8x8 fully connected (28) + 4 chains with two HT devices */
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/* These following are internal definitions */
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#define ROUTETOSELF 0x0F
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#define INVALID_LINK 0xCC /* Used in port list data structure to mark unused data entries.
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Can also be used for no link found in a port list search */
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/* definitions for working with the port list structure */
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#define PORTLIST_TYPE_CPU 0
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#define PORTLIST_TYPE_IO 1
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/*
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* Hypertransport Capability definitions and macros
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*
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*/
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/* HT Host Capability */
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/* bool isHTHostCapability(u32 reg) */
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#define IS_HT_HOST_CAPABILITY(reg) \
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((reg & (u32)0xE00000FF) == (u32)0x20000008)
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#define HT_HOST_CAP_SIZE 0x20
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/* Host CapabilityRegisters */
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#define HTHOST_LINK_CAPABILITY_REG 0x00
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#define HTHOST_LINK_CONTROL_REG 0x04
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#define HTHOST_FREQ_REV_REG 0x08
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#define HT_HOST_REV_REV3 0x60
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#define HTHOST_FEATURE_CAP_REG 0x0C
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#define HTHOST_BUFFER_COUNT_REG 0x10
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#define HTHOST_ISOC_REG 0x14
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#define HTHOST_LINK_TYPE_REG 0x18
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#define HTHOST_TYPE_COHERENT 3
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#define HTHOST_TYPE_NONCOHERENT 7
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#define HTHOST_TYPE_MASK 0x1F
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/* HT Slave Capability (HT1 compat) */
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#define IS_HT_SLAVE_CAPABILITY(reg) \
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((reg & (u32)0xE00000FF) == (u32)0x00000008)
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#define HTSLAVE_LINK01_OFFSET 4
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#define HTSLAVE_LINK_CONTROL_0_REG 4
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#define HTSLAVE_FREQ_REV_0_REG 0xC
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/* HT3 gen Capability */
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#define IS_HT_GEN3_CAPABILITY(reg) \
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((reg & (u32)0xF80000FF) == (u32)0xD0000008)
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#define HTGEN3_LINK01_OFFSET 0x10
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#define HTGEN3_LINK_TRAINING_0_REG 0x10
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/* HT3 Retry Capability */
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#define IS_HT_RETRY_CAPABILITY(reg) \
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((reg & (u32)0xF80000FF) == (u32)0xC0000008)
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#define HTRETRY_CONTROL_REG 4
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/* Unit ID Clumping Capability */
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#define IS_HT_UNITID_CAPABILITY(reg) \
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((reg & (u32)0xF80000FF) == (u32)0x90000008)
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#define HTUNIT_SUPPORT_REG 4
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#define HTUNIT_ENABLE_REG 8
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/*----------------------------------------------------------------------------
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* TYPEDEFS, STRUCTURES, ENUMS
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*
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*----------------------------------------------------------------------------
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*/
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typedef struct cNorthBridge cNorthBridge;
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/* A pair consists of a source node, a link to the destination node, the
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* destination node, and its link back to source node. The even indices are
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* the source nodes and links, and the odd indices are for the destination
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* nodes and links.
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*/
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typedef struct
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{
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/* This section is where the link is in the system and how to find it */
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u8 Type; /* 0 = CPU, 1 = Device, all others reserved */
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u8 Link; /* 0-1 for devices, 0-7 for CPUs */
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u8 NodeID; /* The node, or a pointer to the devices parent node */
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u8 HostLink, HostDepth; /* Link of parent node + depth in chain. Only used by devices */
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SBDFO Pointer; /* A pointer to the device's slave HT capability, so we don't have to keep searching */
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/* This section is for the final settings, which are written to hardware */
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BOOL SelRegang; /* Only used for CPU->CPU links */
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u8 SelWidthIn;
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u8 SelWidthOut;
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u8 SelFrequency;
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/* This section is for keeping track of capabilities and possible configurations */
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BOOL RegangCap;
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u16 PrvFrequencyCap;
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u8 PrvWidthInCap;
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u8 PrvWidthOutCap;
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u16 CompositeFrequencyCap;
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} sPortDescriptor;
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/*
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* Our global state data structure
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*/
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typedef struct {
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AMD_HTBLOCK *HtBlock;
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u8 NodesDiscovered; /* One less than the number of nodes found in the system */
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u8 TotalLinks;
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u8 sysMpCap; /* The maximum number of nodes that all processors are capable of */
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/* Two ports for each link
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* Note: The Port pair 2*N and 2*N+1 are connected together to form a link
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* (e.g. 0,1 and 8,9 are ports on either end of an HT link) The lower number
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* port (2*N) is the source port. The device that owns the source port is
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* always the device closer to the BSP. (i.e. nearer the CPU in a
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* non-coherent chain, or the CPU with the lower NodeID).
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*/
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sPortDescriptor PortList[MAX_PLATFORM_LINKS*2];
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/* The number of coherent links comming off of each node (i.e. the 'Degree' of the node) */
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u8 sysDegree[MAX_NODES];
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/* The systems adjency (sysMatrix[i][j] is true if Node_i has a link to Node_j) */
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BOOL sysMatrix[MAX_NODES][MAX_NODES];
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/* Same as above, but for the currently selected database entry */
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u8 dbDegree[MAX_NODES];
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BOOL dbMatrix[MAX_NODES][MAX_NODES];
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u8 Perm[MAX_NODES]; /* The node mapping from the database to the system */
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u8 ReversePerm[MAX_NODES]; /* The node mapping from the system to the database */
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/* Data for non-coherent initilization */
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u8 AutoBusCurrent;
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u8 UsedCfgMapEntires;
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/* 'This' pointer for northbridge */
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cNorthBridge *nb;
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} sMainData;
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#endif /* H3FFEAT_H */
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