13f66507af
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
73 lines
2.3 KiB
C
73 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/mmio.h>
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#include <gpio.h>
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#include <soc/cdp.h>
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#include <soc/ebi2.h>
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#include <soc/clock.h>
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#include <types.h>
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#include <boardid.h>
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void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count)
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{
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int i;
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for (i = 0; i < count; i++) {
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gpio_tlmm_config(gpio->gpio, gpio->func, gpio->dir,
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gpio->pull, gpio->drvstr, gpio->enable);
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gpio++;
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}
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}
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static void configure_nand_gpio(void)
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{
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/* EBI2 CS, CLE, ALE, WE, OE */
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gpio_tlmm_config(34, 1, 0, GPIO_NO_PULL, GPIO_10MA, GPIO_DISABLE);
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gpio_tlmm_config(35, 1, 0, GPIO_NO_PULL, GPIO_10MA, GPIO_DISABLE);
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gpio_tlmm_config(36, 1, 0, GPIO_NO_PULL, GPIO_10MA, GPIO_DISABLE);
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gpio_tlmm_config(37, 1, 0, GPIO_NO_PULL, GPIO_10MA, GPIO_DISABLE);
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gpio_tlmm_config(38, 1, 0, GPIO_NO_PULL, GPIO_10MA, GPIO_DISABLE);
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/* EBI2 BUSY */
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gpio_tlmm_config(39, 1, 0, GPIO_PULL_UP, GPIO_10MA, GPIO_DISABLE);
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/* EBI2 D7 - D0 */
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gpio_tlmm_config(40, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE);
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gpio_tlmm_config(41, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE);
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gpio_tlmm_config(42, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE);
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gpio_tlmm_config(43, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE);
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gpio_tlmm_config(44, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE);
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gpio_tlmm_config(45, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE);
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gpio_tlmm_config(46, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE);
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gpio_tlmm_config(47, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE);
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}
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void board_nand_init(void)
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{
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struct ebi2cr_regs *ebi2_regs;
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if (board_id() != BOARD_ID_PROTO_0_2_NAND)
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return;
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ebi2_regs = (struct ebi2cr_regs *) EBI2CR_BASE;
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nand_clock_config();
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configure_nand_gpio();
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/* NAND Flash is connected to CS0 */
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clrsetbits_le32(&ebi2_regs->chip_select_cfg0, CS0_CFG_MASK,
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CS0_CFG_SERIAL_FLASH_DEVICE);
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}
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