coreboot-kgpe-d16/src/vendorcode
Julius Werner 2f37bd6551 arm(64): Globally replace writel(v, a) with write32(a, v)
This patch is a raw application of the following spatch to src/:

@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)

BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)

Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21 08:22:28 +02:00
..
amd vendorcode/amd/agesa/f16kb: Enable support for AM1 socket 2015-04-10 15:29:24 +02:00
google arm(64): Globally replace writel(v, a) with write32(a, v) 2015-04-21 08:22:28 +02:00
intel intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP 2015-01-31 23:09:26 +01:00
Kconfig AMD Steppe Eagle: Add binary PI vendorcode files 2014-08-30 19:13:45 +02:00
Makefile.inc Add Intel FSP northbridge support Sandybridge and Ivybridge 2013-12-04 18:45:13 +01:00