439e0d2502
"SPL" from U-Boot is deprecated by bootblock in coreboot/arm, so we don't need it anymore. Change-Id: Id16877075d0b870839a10160073ad70777a2af0a Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2297 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
102 lines
2.1 KiB
Text
102 lines
2.1 KiB
Text
config BOOTBLOCK_CPU_INIT
|
|
string
|
|
default "cpu/samsung/exynos5250/bootblock.c"
|
|
help
|
|
CPU/SoC-specific bootblock code. This is useful if the
|
|
bootblock must load microcode or copy data from ROM before
|
|
searching for the bootblock.
|
|
|
|
config EXYNOS_ACE_SHA
|
|
bool
|
|
default n
|
|
|
|
config SATA_AHCI
|
|
bool
|
|
default n
|
|
|
|
# Example SRAM/iRAM map for Exynos5250 platform:
|
|
#
|
|
# 0x0202_0000: vendor-provided BL1
|
|
# 0x0202_3400: bootblock, assume up to 32KB in size
|
|
# 0x0202_7000: ID section, assume 2KB in size. This will be
|
|
# within the bootblock section.
|
|
# 0x0203_0000: romstage, assume up to 128KB in size.
|
|
# 0x0207_7f00: stack pointer
|
|
|
|
# this may be used to calculate offsets
|
|
config IRAM_BOTTOM
|
|
hex
|
|
default 0x02020000
|
|
|
|
config IRAM_TOP
|
|
hex
|
|
default 0x02077fff
|
|
|
|
config BOOTBLOCK_BASE
|
|
hex
|
|
default 0x02023400
|
|
|
|
config ID_SECTION_BASE
|
|
hex
|
|
default 0x02027e00
|
|
|
|
config ROMSTAGE_BASE
|
|
hex
|
|
default 0x02030000
|
|
|
|
config ROMSTAGE_SIZE
|
|
hex
|
|
default 0x10000
|
|
|
|
config CBFS_ROM_OFFSET
|
|
# Calculated by BL1 + max bootblock size.
|
|
hex "offset of CBFS data in ROM"
|
|
default 0x0A000
|
|
|
|
# TODO Change this to some better address not overlapping bootblock when
|
|
# cbfstool supports creating header in arbitrary location.
|
|
config CBFS_HEADER_ROM_OFFSET
|
|
hex "offset of master CBFS header in ROM"
|
|
default 0x2040
|
|
|
|
# TODO We may probably move this to board-specific implementation files instead
|
|
# of KConfig values.
|
|
config CBFS_CACHE_ADDRESS
|
|
hex "memory address to put CBFS cache data"
|
|
default 0x02060000
|
|
|
|
config CBFS_CACHE_SIZE
|
|
hex "size of CBFS cache data"
|
|
default 0x000017000
|
|
|
|
# FIXME: This is for copying SPI content into SRAM temporarily and
|
|
# will be removed when we have the SPI streaming driver implemented.
|
|
config SPI_IMAGE_HACK
|
|
hex
|
|
default 0x02060000
|
|
|
|
config IRAM_STACK
|
|
hex
|
|
default 0x02077f00
|
|
|
|
# FIXME: other magic numbers that should probably go away
|
|
config XIP_ROM_SIZE
|
|
hex
|
|
default ROMSTAGE_SIZE
|
|
|
|
config SYS_SDRAM_BASE
|
|
hex "SDRAM base address"
|
|
default 0x40000000
|
|
|
|
config SYS_TEXT_BASE
|
|
hex "Executable code section"
|
|
default 0x43e00000
|
|
|
|
config RAMBASE
|
|
hex
|
|
default SYS_SDRAM_BASE
|
|
# according to stefan, this is RAMBASE + 1M.
|
|
config RAMTOP
|
|
hex
|
|
default 0x40100000
|
|
|