Arthur Heymans 8e646e74b3 cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK ... This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Tested on Google peppy (Acer C720). Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, hence BOOTBLOCK_CONSOLE is not yet enabled by default. Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>		2019-04-21 23:31:26 +00:00
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core2	cpu/intel/car: Remove unneeded white space	2019-01-17 13:20:43 +00:00
non-evict	cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK	2019-04-21 23:31:26 +00:00
p3	cpu/intel/car: Remove unneeded white space	2019-01-17 13:20:43 +00:00
p4-netburst	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	2019-03-08 08:33:24 +00:00
bootblock.c	cpu/intel/car/bootblock.c: Report BIST failures	2019-01-08 15:37:18 +00:00
bootblock.h	cpu/intel/car: Enable use of C_ENVIRONMENT_BOOTBLOCK	2019-01-08 15:35:08 +00:00
romstage.c	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	2019-03-08 08:33:24 +00:00