97c5464443
Update processor power limit configuration parameters based on common code base support for Intel Skylake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on nami system Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> |
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.. | ||
acpi | ||
spd | ||
board_info.txt | ||
bootblock_mainboard.c | ||
chromeos.c | ||
chromeos.fmd | ||
cmos.layout | ||
devicetree.cb | ||
dsdt.asl | ||
ec.c | ||
ec.h | ||
gpio.h | ||
Kconfig | ||
Kconfig.name | ||
mainboard.c | ||
Makefile.inc | ||
ramstage.c | ||
romstage.c | ||
smihandler.c |