31be8e403f
In order to build without CONFIG_CONSOLE_SERIAL the Skylake SOC Kconfig should not be enabling serial console by default. Also fix other compile issues when serial console is disabled. BUG=chrome-os-partner:40857 BRANCH=none TEST=build glados without serial console enabled Change-Id: I2b20d9d9cd66e79587525f7bb458782eeeac4a95 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f40fbea8d5dade560c08e4abf15a2a1cc28b9e55 Original-Change-Id: I6c5da8a5eee4090c89deb8feba676479cd834292 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287438 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11043 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
66 lines
1.9 KiB
C
66 lines
1.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <console/uart.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <stdlib.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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static int pch_uart_is_debug(struct device *dev)
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{
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return dev->path.pci.devfn == PCH_DEVFN_UART2;
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}
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static void pch_uart_read_resources(struct device *dev)
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{
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pci_dev_read_resources(dev);
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/* Set the configured UART base address for the debug port */
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if (IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32) &&
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pch_uart_is_debug(dev)) {
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struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
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res->size = 0x1000;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
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IORESOURCE_FIXED;
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}
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}
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static struct device_operations device_ops = {
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.read_resources = &pch_uart_read_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.ops_pci = &soc_pci_ops,
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};
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static const unsigned short pci_device_ids[] = {
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0x9d27, /* UART0 */
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0x9d28, /* UART1 */
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0x9d66, /* UART2 */
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0
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};
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static const struct pci_driver pch_uart __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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