31c6e632cf
Enable L1 Sub-State when both root port and endpoint support it. [pg: keyed the feature to MMCONF_SUPPORT, otherwise boards without that capability fail to build.] Change-Id: Id11fc7c73eb865411747eef63f5f901e00a17f84 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6ac04ad7e2261846e40da297f7fa317ccebda092 Original-BUG=chrome-os-partner:31424 Original-TEST=Build a image and run on Samus proto boards to check if the settings are applied correctly. I just only have proto boards and need someone having EVT boards to confirm the settings. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a Original-Reviewed-on: https://chromium-review.googlesource.com/221436 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/8832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
19 lines
555 B
C
19 lines
555 B
C
#ifndef DEVICE_PCIEXP_H
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#define DEVICE_PCIEXP_H
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/* (c) 2005 Linux Networx GPL see COPYING for details */
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enum aspm_type {
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PCIE_ASPM_NONE = 0,
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PCIE_ASPM_L0S = 1,
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PCIE_ASPM_L1 = 2,
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PCIE_ASPM_BOTH = 3,
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};
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unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
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unsigned int max_devfn, unsigned int max);
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unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);
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extern struct device_operations default_pciexp_ops_bus;
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unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap);
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#endif /* DEVICE_PCIEXP_H */
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