6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
231 lines
7 KiB
C
231 lines
7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include <intelblocks/lpss.h>
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#include <intelblocks/xdci.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/soc_chip.h>
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#include <string.h>
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#include <intelblocks/mp_init.h>
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#include <fsp/ppi/mp_service_ppi.h>
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static void parse_devicetree(FSP_S_CONFIG *params)
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{
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const struct soc_intel_icelake_config *config;
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config = config_of_soc();
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for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
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params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
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for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
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params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
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params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
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params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
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}
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for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
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params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
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}
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static const pci_devfn_t serial_io_dev[] = {
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PCH_DEVFN_I2C0,
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PCH_DEVFN_I2C1,
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PCH_DEVFN_I2C2,
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PCH_DEVFN_I2C3,
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PCH_DEVFN_I2C4,
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PCH_DEVFN_I2C5,
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PCH_DEVFN_GSPI0,
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PCH_DEVFN_GSPI1,
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PCH_DEVFN_GSPI2,
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PCH_DEVFN_UART0,
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PCH_DEVFN_UART1,
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PCH_DEVFN_UART2
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};
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/* UPD parameters to be initialized before SiliconInit */
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void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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{
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int i;
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FSP_S_CONFIG *params = &supd->FspsConfig;
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struct device *dev;
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struct soc_intel_icelake_config *config;
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config = config_of_soc();
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/* Parse device tree and enable/disable devices */
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parse_devicetree(params);
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/* Load VBT before devicetree-specific config. */
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params->GraphicsConfigPtr = (uintptr_t)vbt_get();
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/* Set USB OC pin to 0 first */
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for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++)
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params->Usb2OverCurrentPin[i] = 0;
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for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++)
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params->Usb3OverCurrentPin[i] = 0;
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/* Mandatory to make use of CpuMpPpi implementation from ICL onwards */
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params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
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/* TODO: Remove me as SkipMpInit is getting deprecated */
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params->SkipMpInit = 0;
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mainboard_silicon_init_params(params);
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dev = pcidev_path_on_root(SA_DEVFN_IGD);
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if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
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params->PeiGraphicsPeimInit = 1;
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else
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params->PeiGraphicsPeimInit = 0;
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/* Unlock upper 8 bytes of RTC RAM */
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params->PchLockDownRtcMemoryLock = 0;
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params->CnviBtAudioOffload = config->CnviBtAudioOffload;
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/* SATA */
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dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);
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if (!dev)
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params->SataEnable = 0;
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else {
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params->SataEnable = dev->enabled;
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params->SataMode = config->SataMode;
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params->SataSalpSupport = config->SataSalpSupport;
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memcpy(params->SataPortsEnable, config->SataPortsEnable,
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sizeof(params->SataPortsEnable));
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memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
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sizeof(params->SataPortsDevSlp));
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}
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/* Lan */
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dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6);
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if (!dev)
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params->PchLanEnable = 0;
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else
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params->PchLanEnable = dev->enabled;
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/* Audio */
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params->PchHdaDspEnable = config->PchHdaDspEnable;
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params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
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params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
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params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
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params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
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params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
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params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
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params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
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params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
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params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
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params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
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/* disable Legacy PME */
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memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
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/* Legacy 8254 timer support */
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params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
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params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
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/* S0ix */
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params->PchPmSlpS0Enable = config->s0ix_enable;
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/* USB */
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for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
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params->PortUsb20Enable[i] =
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config->usb2_ports[i].enable;
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params->Usb2OverCurrentPin[i] =
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config->usb2_ports[i].ocpin;
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params->Usb2PhyPetxiset[i] =
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config->usb2_ports[i].pre_emp_bias;
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params->Usb2PhyTxiset[i] =
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config->usb2_ports[i].tx_bias;
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params->Usb2PhyPredeemp[i] =
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config->usb2_ports[i].tx_emp_enable;
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params->Usb2PhyPehalfbit[i] =
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config->usb2_ports[i].pre_emp_bit;
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}
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for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
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params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
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params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
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if (config->usb3_ports[i].tx_de_emp) {
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params->Usb3HsioTxDeEmphEnable[i] = 1;
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params->Usb3HsioTxDeEmph[i] =
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config->usb3_ports[i].tx_de_emp;
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}
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if (config->usb3_ports[i].tx_downscale_amp) {
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params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
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params->Usb3HsioTxDownscaleAmp[i] =
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config->usb3_ports[i].tx_downscale_amp;
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}
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}
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/* Enable xDCI controller if enabled in devicetree and allowed */
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dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
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if (!xdci_can_enable())
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dev->enabled = 0;
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params->XdciEnable = dev->enabled;
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/* PCI Express */
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for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
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if (config->PcieClkSrcUsage[i] == 0)
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config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
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}
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memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
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sizeof(config->PcieClkSrcUsage));
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memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
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sizeof(config->PcieClkSrcClkReq));
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/* eMMC */
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dev = pcidev_on_root(PCH_DEV_SLOT_STORAGE, 0);
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if (!dev)
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params->ScsEmmcEnabled = 0;
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else {
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params->ScsEmmcEnabled = dev->enabled;
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params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
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params->EmmcUseCustomDlls = config->EmmcUseCustomDlls;
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if (config->EmmcUseCustomDlls == 1) {
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params->EmmcTxCmdDelayRegValue =
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config->EmmcTxCmdDelayRegValue;
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params->EmmcTxDataDelay1RegValue =
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config->EmmcTxDataDelay1RegValue;
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params->EmmcTxDataDelay2RegValue =
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config->EmmcTxDataDelay2RegValue;
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params->EmmcRxCmdDataDelay1RegValue =
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config->EmmcRxCmdDataDelay1RegValue;
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params->EmmcRxCmdDataDelay2RegValue =
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config->EmmcRxCmdDataDelay2RegValue;
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params->EmmcRxStrobeDelayRegValue =
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config->EmmcRxStrobeDelayRegValue;
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}
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}
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/* SD */
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dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 5);
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if (!dev)
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params->ScsSdCardEnabled = 0;
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else {
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params->ScsSdCardEnabled = dev->enabled;
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params->SdCardPowerEnableActiveHigh =
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config->SdCardPowerEnableActiveHigh;
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}
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params->Heci3Enabled = config->Heci3Enabled;
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params->Device4Enable = config->Device4Enable;
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}
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/* Mainboard GPIO Configuration */
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__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
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{
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printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
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}
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/* Return list of SOC LPSS controllers */
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const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
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{
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*size = ARRAY_SIZE(serial_io_dev);
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return serial_io_dev;
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}
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