bf72dcbd2f
Use CAPID0_A to provide information closer to reality. * Correctly advertise ECC support, max DIMM count and max capacity * CAPID0_A hasn't changed since SNB, but most EDS mark the bits as reserved even though they are still used by FSP. * Assume the same bits for Tiger Lake as for Ice Lake * Assume the same bits for Skylake as for Coffee Lake * Add CAPID0_A to Icelake headers The lastest complete documentation can be found in Document: 341078-002. Change-Id: I0d8fbb512fccbd99a6cfdacadc496d8266ae4cc7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
68 lines
1.7 KiB
C
68 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <device/pci.h>
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#include <intelblocks/systemagent.h>
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#include <soc/iomap.h>
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#include <soc/systemagent.h>
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/*
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* SoC implementation
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*
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* Add all known fixed memory ranges for Host Controller/Memory
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* controller.
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*/
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void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{
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static const struct sa_mmio_descriptor soc_fixed_resources[] = {
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{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
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"PCIEXBAR" },
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{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
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{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
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{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
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{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
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{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
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/*
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* PMC pci device gets hidden from PCI bus due to Silicon
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* policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with
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* SA resources to ensure that PMCBAR falls under PCI reserved
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* memory range.
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*
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* Note: Don't add any more resource with same offset 0x10
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* under this device space.
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*/
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{ PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE,
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"PMCBAR" },
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};
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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ARRAY_SIZE(soc_fixed_resources));
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}
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/*
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* SoC implementation
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*
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* Perform System Agent Initialization during Ramstage phase.
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*/
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void soc_systemagent_init(struct device *dev)
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{
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/* Enable Power Aware Interrupt Routing */
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enable_power_aware_intr();
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/* Enable BIOS Reset CPL */
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enable_bios_reset_cpl();
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}
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uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
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{
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switch (capid0_a_ddrsz) {
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case 1:
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return 8192;
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case 2:
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return 4096;
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case 3:
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return 2048;
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default:
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return 65536;
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}
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}
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