405721d45c
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
54 lines
1.9 KiB
C
54 lines
1.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2009-2010 iWave Systems
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SCH_PULSBO_H__
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#define __SCH_PULSBO_H__ 1
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int sch_port_access_read(int port, int reg, int bytes);
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void sch_port_access_write(int port, int reg, int bytes, long data);
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void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);
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/* Southbridge IO BARs */
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/* TODO Make sure these don't get changed by stage2 */
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#define SCH_ENABLE_BIT (1<<31)
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#define DEFAULT_ACPIPBLKBASE 0x510
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#define DEFAULT_SMBUSBASE 0x540
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#define DEFAULT_GPIOBASE 0x588
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#define DEFAULT_GPE0BASE 0x5C0
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#define DEFAULT_SMMCNTRLBASE 0x3F703F76
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#define DEFAULT_RCBABASE 0xfed1c000
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#define DEFAULT_PCIEXBAR 0xe0000000 /* 4 KB per PCIe device */
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/* IGD */
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#define GGC 0x52
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/* Root Complex Register Block */
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#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBABASE + x))
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#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBABASE + x))
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#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBABASE + x))
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/* FIXME: should probably be in southbridge, but is setup in romstage, too */
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#define CMC_SHADOW 0x3faf0000
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#endif
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