coreboot-kgpe-d16/src/soc
Andrey Petrov 335384d2b7 soc/intel/xeon_sp: Configure P2SB BAR in bootblock
In order to use early serial output we need to enable P2SB BAR0, because
that allows PCR access to PCH registers.

TEST=tested on OCP Tioga Pass

Change-Id: I476f90b2df67b8045582f0b72dd680dea5a9a275
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-26 02:53:26 +00:00
..
amd amd/common/acpi: move thermal zone to common location 2020-03-25 15:19:52 +00:00
cavium soc: Remove copyright notices 2020-03-18 16:44:46 +00:00
intel soc/intel/xeon_sp: Configure P2SB BAR in bootblock 2020-03-26 02:53:26 +00:00
mediatek soc/mediatek/mt8183: Fix wrong setting of DRS config 2020-03-18 16:47:06 +00:00
nvidia soc: Remove copyright notices 2020-03-18 16:44:46 +00:00
qualcomm soc: Remove copyright notices 2020-03-18 16:44:46 +00:00
rockchip soc: Remove copyright notices 2020-03-18 16:44:46 +00:00
samsung soc: Remove copyright notices 2020-03-18 16:44:46 +00:00
sifive soc: Remove copyright notices 2020-03-18 16:44:46 +00:00
ucb mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. 2019-12-06 15:09:48 +00:00