2871e0e78c
List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
25 lines
466 B
C
25 lines
466 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* This file is created based on Intel Alder Lake Processor PCH Datasheet
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* Document number: 621483
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* Chapter number: 11
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*/
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#include <intelblocks/gspi.h>
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#include <soc/pci_devs.h>
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int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
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{
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switch (gspi_bus) {
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case 0:
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return PCH_DEVFN_GSPI0;
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case 1:
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return PCH_DEVFN_GSPI1;
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case 2:
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return PCH_DEVFN_GSPI2;
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case 3:
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return PCH_DEVFN_GSPI3;
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}
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return -1;
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}
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