349e08535a
Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
59 lines
2 KiB
C
59 lines
2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include "i82801jx.h"
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void i82801jx_early_init(void)
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{
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const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
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/* Set up RCBA. */
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pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1);
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/* Set up PMBASE. */
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pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);
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/* Enable PMBASE. */
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pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80);
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/* Set up GPIOBASE. */
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pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE);
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/* Enable GPIO. */
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pci_write_config8(d31f0, D31F0_GPIO_CNTL,
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pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10);
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/* Reset watchdog. */
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outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */
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outw(0x0002, DEFAULT_TCOBASE + 0x06); /* R/WC, clear second timeout. */
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/* Enable upper 128bytes of CMOS. */
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RCBA32(0x3400) = (1 << 2);
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/* Initialize power management initialization
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register early as it affects reboot behavior. */
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/* Bit 20 activates global reset of host and ME on cf9 writes of 0x6
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and 0xe (required if ME is disabled but present), bit 31 locks it.
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The other bits are 'must write'. */
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u8 reg8 = pci_read_config8(d31f0, 0xac);
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reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8);
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pci_write_config8(d31f0, 0xac, reg8);
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/* TODO: If RTC power failed, reset RTC state machine
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(set, then reset RTC 0x0b bit7) */
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/* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2)
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before they get cleared. */
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}
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