Felix Held 34fc29ae96 soc/amd: add and use fch_enable_hpet_decode ... On Picasso we missed setting this bit in coreboot and since the default after reset is 0, we had to rely on the FSP to set this bit. Stoneyridge and Cezanne have the HPET decode enable bit in the same position in the same register. In the ACPI table entry written by southbridge_write_acpi_tables the HPET entry gets added, so we should make sure that we enable the decode. TEST=HPET still works on Mandolin. Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50512 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-02-12 20:49:10 +00:00
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acpi	soc/amd/common: Notify SMU of AC/DC state upon resume	2021-01-27 10:24:36 +00:00
block	soc/amd: add and use fch_enable_hpet_decode	2021-02-12 20:49:10 +00:00
fsp	soc/amd/picasso: move chipset_handle_reset to common	2020-12-11 17:44:19 +00:00
vboot	soc/amd/common/vboot: use transfer_buffer_valid function	2020-11-30 16:29:14 +00:00
Kconfig.common	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00
Makefile.inc	soc/amd/picasso: move chipset_handle_reset to common	2020-12-11 17:44:19 +00:00