coreboot-kgpe-d16/src/mainboard/google/veyron/Kconfig
Philipp Deppenwiese c07f8fbe6f security/tpm: Unify the coreboot TPM software stack
* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
  * MAINBOARD_HAS_*_TPM # * BUS driver
  * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
  * Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.

Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04 20:33:07 +00:00

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##
## This file is part of the coreboot project.
##
## Copyright 2014 Rockchip Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config BOARD_GOOGLE_VEYRON # dummy option to be selected by variant boards
def_bool n
if BOARD_GOOGLE_VEYRON
# Some Veyron boards incorrectly had their RAM code strapped with 100Kohm
# resistors. These get overpowered by the SoC's internal pull-downs, so we
# cannot read those pins as tri-state. They're restricted to binary RAM codes.
config VEYRON_FORCE_BINARY_RAM_CODE
bool
default y if BOARD_GOOGLE_VEYRON_JAQ
default y if BOARD_GOOGLE_VEYRON_JERRY
default y if BOARD_GOOGLE_VEYRON_MIGHTY
default n
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select COMMON_CBFS_SPI_WRAPPER
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_SPI
select SOC_ROCKCHIP_RK3288
select MAINBOARD_HAS_CHROMEOS
select BOARD_ROMSIZE_KB_4096
select HAVE_HARD_RESET
select SPI_FLASH
select SPI_FLASH_GIGADEVICE
select SPI_FLASH_WINBOND
select MAINBOARD_HAS_I2C_TPM_GENERIC
select MAINBOARD_HAS_TPM1
config VBOOT
select VBOOT_VBNV_EC
config MAINBOARD_DIR
string
default google/veyron
config MAINBOARD_PART_NUMBER
string
default "Veyron_Jaq" if BOARD_GOOGLE_VEYRON_JAQ
default "Veyron_Jerry" if BOARD_GOOGLE_VEYRON_JERRY
default "Veyron_Mighty" if BOARD_GOOGLE_VEYRON_MIGHTY
default "Veyron_Minnie" if BOARD_GOOGLE_VEYRON_MINNIE
default "Veyron_Speedy" if BOARD_GOOGLE_VEYRON_SPEEDY
default "Veyron"
config MAINBOARD_VENDOR
string
default "Google"
config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
default 0x0
config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
int
default 100
config BOOT_DEVICE_SPI_FLASH_BUS
int
default 2
config DRIVER_TPM_I2C_BUS
hex
default 0x1
config DRIVER_TPM_I2C_ADDR
hex
default 0x20
config CONSOLE_SERIAL_UART_ADDRESS
hex
depends on DRIVERS_UART
default 0xFF690000
config PMIC_BUS
int
default 0
config CBFS_SIZE
hex
default 0x100000 if CHROMEOS
default ROM_SIZE
config EC_GOOGLE_CHROMEEC_BOARDNAME
string
depends on CHROMEOS
#default "jaq" if BOARD_GOOGLE_VEYRON_JAQ
default "jerry" if BOARD_GOOGLE_VEYRON_JERRY
#default "mighty" if BOARD_GOOGLE_VEYRON_MIGHTY
#default "minnie" if BOARD_GOOGLE_VEYRON_MINNIE
#default "speedy" if BOARD_GOOGLE_VEYRON_SPEEDY
config GBB_HWID
string
depends on CHROMEOS
default "JAQ TEST A-A 8292" if BOARD_GOOGLE_VEYRON_JAQ
default "JERRY TEST A-A 1250" if BOARD_GOOGLE_VEYRON_JERRY
default "MIGHTY TEST A-A 4557" if BOARD_GOOGLE_VEYRON_MIGHTY
default "MINNIE TEST A-A 5151" if BOARD_GOOGLE_VEYRON_MINNIE
default "SPEEDY TEST A-A 8421" if BOARD_GOOGLE_VEYRON_SPEEDY
endif # BOARD_GOOGLE_VEYRON