311 lines
7.5 KiB
C
311 lines
7.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _AMD_FW_TOOL_H_
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#define _AMD_FW_TOOL_H_
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#include <stdint.h>
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#include <stdbool.h>
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typedef enum _amd_fw_type {
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AMD_FW_PSP_PUBKEY = 0,
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AMD_FW_PSP_BOOTLOADER = 1,
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AMD_FW_PSP_SMU_FIRMWARE = 8,
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AMD_FW_PSP_RECOVERY = 3,
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AMD_FW_PSP_RTM_PUBKEY = 5,
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AMD_FW_PSP_SECURED_OS = 2,
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AMD_FW_PSP_NVRAM = 4,
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AMD_FW_PSP_SECURED_DEBUG = 9,
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AMD_FW_PSP_TRUSTLETS = 12,
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AMD_FW_PSP_TRUSTLETKEY = 13,
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AMD_FW_PSP_SMU_FIRMWARE2 = 18,
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AMD_PSP_FUSE_CHAIN = 11,
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AMD_FW_PSP_SMUSCS = 95,
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AMD_DEBUG_UNLOCK = 0x13,
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AMD_HW_IPCFG = 0x20,
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AMD_WRAPPED_IKEK = 0x21,
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AMD_TOKEN_UNLOCK = 0x22,
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AMD_SEC_GASKET = 0x24,
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AMD_MP2_FW = 0x25,
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AMD_DRIVER_ENTRIES = 0x28,
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AMD_FW_KVM_IMAGE = 0x29,
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AMD_S0I3_DRIVER = 0x2d,
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AMD_ABL0 = 0x30,
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AMD_ABL1 = 0x31,
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AMD_ABL2 = 0x32,
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AMD_ABL3 = 0x33,
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AMD_ABL4 = 0x34,
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AMD_ABL5 = 0x35,
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AMD_ABL6 = 0x36,
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AMD_ABL7 = 0x37,
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AMD_FW_PSP_WHITELIST = 0x3a,
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AMD_VBIOS_BTLOADER = 0x3c,
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AMD_FW_L2_PTR = 0x40,
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AMD_FW_USB_PHY = 0x44,
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AMD_FW_TOS_SEC_POLICY = 0x45,
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AMD_FW_DRTM_TA = 0x47,
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AMD_FW_RECOVERYAB_A = 0x48,
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AMD_FW_RECOVERYAB_B = 0x4A,
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AMD_FW_BIOS_TABLE = 0x49,
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AMD_FW_KEYDB_BL = 0x50,
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AMD_FW_KEYDB_TOS = 0x51,
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AMD_FW_PSP_VERSTAGE = 0x52,
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AMD_FW_VERSTAGE_SIG = 0x53,
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AMD_RPMC_NVRAM = 0x54,
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AMD_FW_SPL = 0x55,
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AMD_FW_DMCU_ERAM = 0x58,
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AMD_FW_DMCU_ISR = 0x59,
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AMD_FW_MSMU = 0x5a,
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AMD_FW_SPIROM_CFG = 0x5c,
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AMD_FW_DMCUB = 0x71,
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AMD_FW_PSP_BOOTLOADER_AB = 0x73,
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AMD_TA_IKEK = 0x8d,
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AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */
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AMD_FW_GEC,
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AMD_FW_XHCI,
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AMD_FW_INVALID, /* Real last one to detect the last entry in table. */
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AMD_FW_SKIP /* This is for non-applicable options. */
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} amd_fw_type;
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typedef enum _amd_bios_type {
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AMD_BIOS_RTM_PUBKEY = 0x05,
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AMD_BIOS_SIG = 0x07,
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AMD_BIOS_APCB = 0x60,
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AMD_BIOS_APOB = 0x61,
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AMD_BIOS_BIN = 0x62,
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AMD_BIOS_APOB_NV = 0x63,
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AMD_BIOS_PMUI = 0x64,
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AMD_BIOS_PMUD = 0x65,
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AMD_BIOS_UCODE = 0x66,
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AMD_BIOS_APCB_BK = 0x68,
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AMD_BIOS_MP2_CFG = 0x6a,
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AMD_BIOS_PSP_SHARED_MEM = 0x6b,
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AMD_BIOS_L2_PTR = 0x70,
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AMD_BIOS_INVALID,
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AMD_BIOS_SKIP
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} amd_bios_type;
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typedef enum _amd_addr_mode {
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AMD_ADDR_PHYSICAL = 0, /* Physical address */
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AMD_ADDR_REL_BIOS, /* Relative to beginning of image */
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AMD_ADDR_REL_TAB, /* Relative to table */
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AMD_ADDR_REL_SLOT, /* Relative to slot */
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} amd_addr_mode;
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struct second_gen_efs { /* todo: expand for Server products */
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int gen:1; /* Client products only use bit 0 */
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int reserved:31;
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} __attribute__((packed));
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#define EFS_SECOND_GEN 0
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#define EFS_BEFORE_SECOND_GEN 1
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typedef struct _embedded_firmware {
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uint32_t signature; /* 0x55aa55aa */
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uint32_t imc_entry;
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uint32_t gec_entry;
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uint32_t xhci_entry;
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uint32_t psp_directory;
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union {
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uint32_t new_psp_directory;
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uint32_t combo_psp_directory;
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};
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uint32_t bios0_entry; /* todo: add way to select correct entry */
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uint32_t bios1_entry;
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uint32_t bios2_entry;
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struct second_gen_efs efs_gen;
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uint32_t bios3_entry;
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uint32_t reserved_2Ch;
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uint32_t promontory_fw_ptr;
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uint32_t lp_promontory_fw_ptr;
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uint32_t reserved_38h;
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uint32_t reserved_3Ch;
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uint8_t spi_readmode_f15_mod_60_6f;
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uint8_t fast_speed_new_f15_mod_60_6f;
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uint8_t reserved_42h;
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uint8_t spi_readmode_f17_mod_00_2f;
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uint8_t spi_fastspeed_f17_mod_00_2f;
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uint8_t qpr_dummy_cycle_f17_mod_00_2f;
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uint8_t reserved_46h;
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uint8_t spi_readmode_f17_mod_30_3f;
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uint8_t spi_fastspeed_f17_mod_30_3f;
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uint8_t micron_detect_f17_mod_30_3f;
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uint8_t reserved_4Ah;
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uint8_t reserved_4Bh;
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uint32_t reserved_4Ch;
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} __attribute__((packed, aligned(16))) embedded_firmware;
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typedef struct _psp_directory_header {
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uint32_t cookie;
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uint32_t checksum;
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uint32_t num_entries;
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union {
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uint32_t additional_info;
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struct {
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uint32_t dir_size:10;
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uint32_t spi_block_size:4;
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uint32_t base_addr:15;
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uint32_t address_mode:2;
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uint32_t not_used:1;
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} __attribute__((packed)) additional_info_fields;
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};
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} __attribute__((packed, aligned(16))) psp_directory_header;
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typedef struct _psp_directory_entry {
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uint8_t type;
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uint8_t subprog;
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uint16_t rsvd;
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uint32_t size;
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uint64_t addr:62; /* or a value in some cases */
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uint64_t address_mode:2;
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} __attribute__((packed)) psp_directory_entry;
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typedef struct _psp_directory_table {
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psp_directory_header header;
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psp_directory_entry entries[];
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} __attribute__((packed, aligned(16))) psp_directory_table;
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#define MAX_PSP_ENTRIES 0x2f
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typedef struct _psp_combo_header {
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uint32_t cookie;
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uint32_t checksum;
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uint32_t num_entries;
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uint32_t lookup;
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uint64_t reserved[2];
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} __attribute__((packed, aligned(16))) psp_combo_header;
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typedef struct _psp_combo_entry {
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uint32_t id_sel;
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uint32_t id;
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uint64_t lvl2_addr;
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} __attribute__((packed)) psp_combo_entry;
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typedef struct _psp_combo_directory {
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psp_combo_header header;
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psp_combo_entry entries[];
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} __attribute__((packed, aligned(16))) psp_combo_directory;
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#define MAX_COMBO_ENTRIES 1
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typedef struct _bios_directory_hdr {
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uint32_t cookie;
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uint32_t checksum;
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uint32_t num_entries;
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union {
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uint32_t additional_info;
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struct {
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uint32_t dir_size:10;
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uint32_t spi_block_size:4;
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uint32_t base_addr:15;
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uint32_t address_mode:2;
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uint32_t not_used:1;
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} __attribute__((packed)) additional_info_fields;
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};
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} __attribute__((packed, aligned(16))) bios_directory_hdr;
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typedef struct _bios_directory_entry {
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uint8_t type;
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uint8_t region_type;
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int reset:1;
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int copy:1;
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int ro:1;
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int compressed:1;
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int inst:4;
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uint8_t subprog; /* b[7:3] reserved */
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uint32_t size;
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uint64_t source:62;
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uint64_t address_mode:2;
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uint64_t dest;
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} __attribute__((packed)) bios_directory_entry;
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typedef struct _bios_directory_table {
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bios_directory_hdr header;
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bios_directory_entry entries[];
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} bios_directory_table;
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#define MAX_BIOS_ENTRIES 0x2f
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#define BDT_LVL1 (1 << 0)
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#define BDT_LVL2 (1 << 1)
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#define BDT_LVL1_AB (1 << 2)
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#define BDT_LVL2_AB (1 << 3)
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#define BDT_BOTH (BDT_LVL1 | BDT_LVL2)
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#define BDT_BOTH_AB (BDT_LVL1_AB | BDT_LVL2_AB)
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typedef struct _amd_bios_entry {
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amd_bios_type type;
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char *filename;
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int subpr;
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int region_type;
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int reset;
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int copy;
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int ro;
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int zlib;
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int inst;
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uint64_t src;
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uint64_t dest;
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size_t size;
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int level;
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} amd_bios_entry;
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typedef struct _ish_directory_table {
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uint32_t checksum;
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uint32_t boot_priority;
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uint32_t update_retry_count;
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uint8_t glitch_retry_count;
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uint8_t glitch_higherbits_reserved[3];
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uint32_t pl2_location;
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uint32_t psp_id;
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uint32_t slot_max_size;
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uint32_t reserved;
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} __attribute__((packed)) ish_directory_table;
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#define EMBEDDED_FW_SIGNATURE 0x55aa55aa
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#define PSP_COOKIE 0x50535024 /* 'PSP$' */
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#define PSPL2_COOKIE 0x324c5024 /* '2LP$' */
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#define PSP2_COOKIE 0x50535032 /* 'PSP2' */
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#define BHD_COOKIE 0x44484224 /* 'DHB$ */
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#define BHDL2_COOKIE 0x324c4224 /* '2LB$ */
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#define PSP_LVL1 (1 << 0)
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#define PSP_LVL2 (1 << 1)
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#define PSP_LVL1_AB (1 << 2)
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#define PSP_LVL2_AB (1 << 3)
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#define PSP_BOTH (PSP_LVL1 | PSP_LVL2)
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#define PSP_BOTH_AB (PSP_LVL1_AB | PSP_LVL2_AB)
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typedef struct _amd_fw_entry {
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amd_fw_type type;
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char *filename;
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uint8_t subprog;
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uint64_t dest;
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size_t size;
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int level;
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uint64_t other;
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} amd_fw_entry;
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typedef struct _amd_cb_config {
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bool have_whitelist;
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bool unlock_secure;
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bool use_secureos;
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bool load_mp2_fw;
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bool multi_level;
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bool s0i3;
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bool second_gen;
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bool have_mb_spl;
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bool recovery_ab;
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bool recovery_ab_single_copy;
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bool need_ish;
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bool use_combo;
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} amd_cb_config;
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void register_fw_fuse(char *str);
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uint8_t process_config(FILE *config, amd_cb_config *cb_config, uint8_t print_deps);
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#define OK 0
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#define LINE_EOF (1)
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#define LINE_TOO_LONG (2)
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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#endif /* _AMD_FW_TOOL_H_ */
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