a2fe7789e9
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
59 lines
1.8 KiB
C
59 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/irq.h>
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#include <soc/pci_devs.h>
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#include <soc/pmc.h>
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#define PCI_DEV_PIRQ_ROUTES \
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PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
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PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \
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PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
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PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
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#define PIRQ_PIC_ROUTES \
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PIRQ_PIC(A, DISABLE), \
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PIRQ_PIC(B, DISABLE), \
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PIRQ_PIC(C, DISABLE), \
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PIRQ_PIC(D, DISABLE), \
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PIRQ_PIC(E, DISABLE), \
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PIRQ_PIC(F, DISABLE), \
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PIRQ_PIC(G, DISABLE), \
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PIRQ_PIC(H, DISABLE)
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/* CORE bank DIRQs - up to 16 supported */
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#define TPAD_IRQ_OFFSET 0
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#define TOUCH_IRQ_OFFSET 1
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#define I8042_IRQ_OFFSET 2
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#define ALS_IRQ_OFFSET 3
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/* Corresponding SCORE GPIO pins */
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#define TPAD_IRQ_GPIO 55
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#define TOUCH_IRQ_GPIO 72
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#define I8042_IRQ_GPIO 101
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#define ALS_IRQ_GPIO 70
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/* SUS bank DIRQs - up to 16 supported */
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#define CODEC_IRQ_OFFSET 0
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/* Corresponding SUS GPIO pins */
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#define CODEC_IRQ_GPIO 9
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